Te-Yuan
Te-Yuan Chung, Pingtung County TW
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20130136151 | HIGHLY ADAPTIVE THERMAL PROPERTIES MEASUREMENT SYSTEM AND MEASURING METHOD THEREOF - A highly adaptive thermal properties measurement system and measuring method thereof, for measuring various thermal property values of a device under test without actually lighting up the device under test, are disclosed. The measurement system includes a light source unit, a light modulation module, a holding unit, a thermal reflection unit, a thermal signal capture unit, and a control and computation unit. A light field provided from the light source unit is first modulated by the light modulation module for its distribution of intensity, and then illuminates on the device under test such that the device under test is heated in a specific mode so as to simulate a temperature distribution of the device under test in a state of continuous operation. Further, the control and computation unit computes various thermal property values of the device under test based on a top-surface thermal signal and a bottom-surface thermal signal captured by the thermal signal capture unit. | 05-30-2013 |
Te-Yuan Chung, Jhongli City TW
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20150060033 | COOLING SYSTEM WITH A PASSIVE HEAT DISSIPATION STRUCTURE - The present invention discloses a cooling system with a passive heat dissipation structure, the cooling system includes plural heat conducting pipes, and a shielding tube included to surround the heat conducting pipes. The heat generated from a heat source placed below the cooling system heats the surrounding fluid (air) and turns it into heated fluid. The heated fluid is lower in density and is dissipated away through convection by the heat conducting pipes, leaves its original space to cooler fluid (at room temperature). The mixing of the heated fluid with the cooler fluid can be prevented by the heat conducting pipes, and the heat convection of the heat source by the cooler fluid is increased. With the implementation of the present invention, the benefits of easy implementing, easy to use, requiring no extra energy and saving costs are achieved, and the heat of the heat source is promptly dissipated away. | 03-05-2015 |
Te-Yuan Chung, Jhongli TW
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20110259421 | PHOTOVOLTAIC MODULE HAVING CONCENTRATOR - A photovoltaic module with reduced size is provided. The photovoltaic module includes two wedged concentrator components and a solar cell structure. The first wedged concentrator component is positioned on the second wedged concentrator component. The solar cell structure is mounted on a quadrilateral lateral surface of the first wedged concentrator component for receiving light from the first wedged concentrator component through the quadrilateral lateral surface. The wedge structure of the concentrator components causes total internal reflection of the light on a top surface of the first wedged concentrator component when the light travels within the first wedged concentrator component from a bottom surface to the quadrilateral lateral surface. A diffractive optics element is provided in the second wedged concentrator component to contribute the total internal reflection in the first wedged concentrator component. | 10-27-2011 |
Te-Yuan Chung, Jhongli Ctiy TW
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20150060017 | COOLING APPARATUS USING SOLID-LIQUID PHASE CHANGE MATERIAL - A cooling apparatus using solid-liquid phase change material (solid-liquid PCM) is disclosed. The cooling apparatus includes a pipeline, a housing enclosing the pipeline, and the solid-liquid PCM filling in an interior of the pipeline and a space between the pipeline and the housing. The solid-liquid PCM can contact a heat source and absorb the heat generated by the heat source, so as to transform from solid state to liquid state. The solid-liquid PCM in the liquid state can circulate inside the pipeline and the space between the pipeline and the housing. Thus, the heat is dissipated by the means of thermal convection. Meanwhile, the heat also can be dissipated through the housing. Therefore, the heat dissipation can be achieved by thermal conduction and heat convection simultaneously. | 03-05-2015 |
Te-Yuan Huang, Taipei TW
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20100303129 | FREQUENCY HOPPING METHOD FOR LOCALIZATION SYSTEM - A frequency hopping method for localization system is aimed to overcome the degradation of location accuracy due to radio interference if there are some other radio devices using the same radio frequency as a localization system. A Packet Reception Rate (PRR) thresholding or a learning-based approach for the diagnostic test is proposed. In that, a PRR thresholding or a set of parameters trained by Hidden Markov Model (HMM) is used as a criterion to decide whether or not to hop. The proposed hopping mechanism provides an accurate and stable localization with a minimum delay. | 12-02-2010 |
Te-Yuan Li, Hualien County TW
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20090273812 | METHOD FOR HALFTONE IMAGE TRANSFORMATION, PRINTING AND HALFTONE MASK GENERATION - A printing method for printing an input image. Firstly, a halftone mask is generated. The input image is transformed into a halftone image through the halftone mask. The halftone image is then output for printing. The halftone mask is an array of N elements, and the following steps generate the halftone mask. An initial array of N elements is first provided. Thereafter, a first value is selectively assigned to an element in the initial array to generate a first array. The second to the N | 11-05-2009 |
Te-Yuan Wu, Hsinchu TW
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20140319693 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias. | 10-30-2014 |
Te-Yuan Wu, Hsinchu City TW
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20120313175 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground. | 12-13-2012 |
20120319189 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE - The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type. | 12-20-2012 |
20130113048 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively. | 05-09-2013 |
20130187225 | HIGH VOLTAGE MOSFET DEVICE - A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%. | 07-25-2013 |
20130234141 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged. | 09-12-2013 |
20130277742 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. | 10-24-2013 |
20130307071 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN THEREOF - A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region further includes a plurality of third doped regions, a plurality of gaps, and a plurality of fourth doped regions. The gaps and the third doped regions s are alternately arranged, and the fourth doped regions are formed in the gaps. The third doped regions include a second conductivity type complementary to the first conductivity type, and the fourth doped regions include the first conductivity type. | 11-21-2013 |
20140367805 | MEMS structure and method of forming the same - A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer. | 12-18-2014 |
20150079754 | METHOD OF FABRICATING HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well. | 03-19-2015 |
Te-Yuan Yin, Hsinchu City TW
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20160111295 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. The method includes the following steps. A substrate including a memory cell region and a peripheral region is provided, and a plurality of isolation structures are formed in the substrate. Each of the isolation structures contains an exposed portion protruding beyond the surface of the substrate. A first dielectric layer is formed on the substrate. A protective layer is formed on a sidewall of the exposed portion of each of the isolation structures. The first dielectric layer on the peripheral region is removed. A second dielectric layer is formed on the substrate of the peripheral region. | 04-21-2016 |