Te-Wei Chen
Te-Wei Chen, Zhubei City TW
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20110089535 | Electrostatic Discharge Protection Device - The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively. | 04-21-2011 |
20150098159 | ESD PROTECTION CIRCUIT AND ESD PROTECTION METHOD THEREOF - The present invention provides an ESD protection circuit including a discharge transistor, a first switch, a second switch, a third switch and a fourth switch. The discharge transistor forms a discharge path between a first voltage terminal and a second voltage terminal. The first switch selectively provides voltage at the first voltage terminal to a control terminal of the discharge transistor. The second switch selectively provides voltage at the second voltage terminal to the control terminal of the discharge transistor. The third switch selectively provides voltage at the first voltage terminal to a substrate of the discharge transistor. The fourth switch selectively provides voltage at second voltage terminal to the substrate of the discharge transistor. | 04-09-2015 |
Te-Wei Chen, Hsinchu County TW
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20100308470 | SEMICONDUCTOR DEVICE AND INDUCTOR - A semiconductor device and an inductor are provided. The semiconductor device includes a top level interconnect metal layer (M | 12-09-2010 |
Te-Wei Chen, Taipei City TW
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20100178037 | DISPLAY APPARATUS, VIDEO GENERATION APPARATUS, AND METHOD THEREOF - A video generation apparatus for processing a video source to generate a video stream supplied to a display apparatus comprises: a buffer and a scaler. The buffer is capable of storing scaling reference lines retrieved from the video source. The scaler is used for generating scaled lines based on the scaling reference lines stored in the buffer, wherein the scaled lines are used in the video stream supplied to the display apparatus, and an input line period length of the scaler receiving the video source and an output line period length of the scaler supplying the video stream to the display apparatus are the same. Valid scaled lines generated for each frame by the scaler is less than a total number of output line periods for each frame of the video stream. | 07-15-2010 |
20100265246 | DISPLAY CONTROL DEVICE FOR FLAT PANEL DISPLAYS AND DISPLAY DEVICE UTILIZING THE SAME - A display control device for a flat panel display is provided and includes a display controller and a timing controller. The display controller is provided for receiving an input signal and generating a display signal and a plurality of timing signals corresponding to the display signal. The timing controller includes a timing control unit and a data processing unit. The timing control unit is coupled to the display controller for providing a plurality of control signals required for the flat panel display. The data processing unit is incorporated into the display controller in a first integrated circuit chip for receiving the display signal and generating a plurality of output signals in synchronization with the timing signals. The output signals are output to the flat panel display through a predetermined interface. | 10-21-2010 |
Te-Wei Chen, Tainan City TW
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20100227401 | MEDIA AND PROCESSES FOR THE EX VIVO PRODUCTION OF MEGAKARYOCYTES FROM HUMAN CD34+ CELLS - Disclosed herein are media and processes for the ex vivo production of megakaryocytes from human CD34 | 09-09-2010 |
Te-Wei Chen, Chu-Pei City TW
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20080315854 | Input/Output Regulating Circuitry with Self-Electrostatic-Discharge Protection - An I/O regulating circuitry is provided. The I/O regulating circuitry omits the ESD device in a CMOS process with a minimized critical dimension to reduce chip size while still maintaining electrostatic discharge immunity. The I/O regulating circuitry is applied in MLC flash memory applications and the flash controller thereof. | 12-25-2008 |
20100006943 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device for providing an ESD path between two circuitries is provided. Each circuitry has a power supply terminal and a ground terminal. The protection device comprises an equivalent MOS, a first terminal, and a second terminal. The equivalent MOS comprises a source, a drain and a gate, wherein the drain is connected to the gate. The first terminal is connected to the gate, while the second terminal is connected to the source. The first terminal is connected to one power supply terminal and ground terminal, whereas the second terminal is connected to the other the power supply terminal and ground terminal. | 01-14-2010 |
Te-Wei Chen, Chu-Pei City CN
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20100008003 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device for providing an ESD path between two circuitries is provided. Each circuitry has a power supply terminal and a ground terminal. The protection device comprises an equivalent MOS, a first terminal, and a second terminal. The equivalent MOS comprises a source, a drain and a gate, wherein the drain is connected to the gate. The first terminal is connected to the gate, while the second terminal is connected to the source. The first terminal is connected to one power supply terminal and ground terminal, whereas the second terminal is connected to the other the power supply terminal and ground terminal. | 01-14-2010 |
Te-Wei Chen, Chupei City TW
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20090147601 | Non-volatile memory structure - A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line is placed across the n bit lines. Each of the repair circuits is electrically connected between the corresponding bit line and the sense amplifier. M and N are natural number. | 06-11-2009 |
Te-Wei Chen, Taiwan CN
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20150241441 | Hydrophilic Film, Preparation Method and Applications Thereof - The present invention provides a hydrophilic film that causes a liquid to diffuse rapidly in a single direction. The hydrophilic film comprises a substrate having a texture of parallel sunken and raised patterns, and a hydrophilic coat comprising a coat of silicon dioxide particles. The present invention also provides a method for preparing the hydrophilic film. The method comprises: preparing an aqueous dispersion of silicon dioxide particles, wherein the average size of the silicon dioxide particles is 1 to 60 nm, and the concentration of the silicon dioxide particles is 0.05% to 15% by weight; coating the aqueous dispersion of silicon dioxide particles on a substrate, wherein the substrate has a texture of parallel sunken and raised patterns; and drying the substrate coated with the aqueous dispersion of silicon dioxide particles. | 08-27-2015 |