Patent application number | Description | Published |
20110221632 | High-precision radio frequency ranging system - Methods for estimating a distance between an originator and a transponder, methods for calculating a fine time adjustment in a radio, computer-readable storage media containing instructions to configure a processor to perform such methods, originators used in a system for estimating a distance to a transponder, and transponders used in a system for estimating a distance to an originator. The methods utilize fine time adjustments to achieve sub-clock cycle time resolution. The methods may utilize offset master clocks. The methods may utilize a round-trip full-duplex configuration or a round-trip full-duplex configuration. The method produces accurate estimates of the distance between two radios. | 09-15-2011 |
20120019413 | System and method for real-time locating - A locating system, includes at least one initiator configured to operate at a first clock frequency, and to transmit a measurement signal including a first preamble; and at least one transponder configured to operate at a second clock frequency, to receive the measurement signal, and to transmit a response signal to the initiator, the response signal including a second preamble. The initiator is further configured to calculate, based on the response signal, a distance between the initiator and the transponder for determining a location of the transponder. | 01-26-2012 |
20120133558 | High-Precision Radio Frequency Ranging System - Methods for estimating a distance between an originator and a transponder, methods for calculating a fine time adjustment in a radio, computer-readable storage media containing instructions to configure a processor to perform such methods, originators used in a system for estimating a distance to a transponder, and transponders used in a system for estimating a distance to an originator. The methods utilize fine time adjustments to achieve sub-clock cycle time resolution. The methods may utilize offset master clocks. The methods may utilize a round-trip full-duplex configuration or a round-trip half-duplex configuration. The method produces accurate estimates of the distance between two radios. | 05-31-2012 |
20140203971 | SYSTEM AND METHOD FOR TRACKING AND LOCATING A PERSON, ANIMAL, OR MACHINE - A system and method for estimating the position of an object, such as a person, animal, or machine. The system includes first and second inertial measurement units, a first and second originator antennas, and a first and second transponder antennas. The system uses data from the inertial measurement units to estimate a position of the object. The system also calculates a range measurement between the first originator antenna and first transponder antenna. The system calculates a first CPD measurement between the second transponder antenna and the first originator antenna, and a second CPD measurement between the second originator antenna and the first transponder antenna. The range measurement and at least one CPD measurement are used to update a Kalman filter for estimating the position of the object. The system determines also updates the Kalman filter when one of the inertial measurement units is in a zero-velocity condition. | 07-24-2014 |
20140207374 | SYSTEM AND METHOD FOR TRACKING AND LOCATING A PERSON, ANIMAL, OR MACHINE - A system and method for estimating the position of an object, such as a person, animal, or machine. The system includes first and second inertial measurement units, a first and second originator antennas, and a first and second transponder antennas. The system uses data from the inertial measurement units to estimate a position of the object. The system also calculates a range measurement between the first originator antenna and first transponder antenna. The system calculates a first CPD measurement between the second transponder antenna and the first originator antenna, and a second CPD measurement between the second originator antenna and the first transponder antenna. The range measurement and at least one CPD measurement are used to update a Kalman filter for estimating the position of the object. The system determines also updates the Kalman filter when one of the inertial measurement units is in a zero-velocity condition. | 07-24-2014 |
20140266907 | Geolocation with Radio-Frequency Ranging - A geolocation system includes an originator device configured to transmit a first wireless signal to a transponder device. The transponder device is configured to transmit a second wireless signal to the originator device. The system includes at least one observer device configured to receive the first wireless signal from the originator device and receive the second wireless signal from the transponder device. The system also includes a first processor configured to calculate a transactional difference range at the at least one observer device based on the first wireless signal received at the observer device and the second wireless signal received at the observer device. A corrected transactional difference range value may be calculated by subtracting a time-of-flight of the first wireless signal from the originator device to the transponder device from the transactional difference range. A method of performing geolocation using a transactional difference range is also disclosed. | 09-18-2014 |
20150346332 | UNWRAPPING AND PREDICTION OF DISTANCE AND VELOCITY MEASUREMENTS USING CARRIER SIGNALS - Systems and methods for performing distance and velocity measurements, such as by using carrier signals, are disclosed. A measurement method may include transmitting a first signal from an originator device to a transponder device and determining a carrier phase of the first signal at the transponder device. The measurement method may also include transmitting a second signal from the transponder device to the originator device and determining a carrier phase of the second signal at the originator device. The measurement method may include estimating a relative distance between the originator device and the transponder device using the carrier phase of the first carrier signal, the carrier phase of the second carrier signal. The method may also include estimating the relative distance using a frequency difference. The method may include using an adjusted relative distance to determine a total distance between the originator device and the transponder device. | 12-03-2015 |
20150346349 | CARRIER PHASE DISTANCE AND VELOCITY MEASUREMENTS - Systems and methods for performing distance and velocity measurements, such as by using carrier signals, are disclosed. A measurement system device may include a first antenna configured to receive a first signal from a transmitting device, the first signal having a carrier frequency, and a second antenna configured to receive the first signal from the transmitting device. The measurement system device may also include a processor configured to determine a first differential distance between the first antenna and the second antenna from the transmitting device and to determine a rate of change of the first differential distance. The processor may also be configured to estimate a geometry of the measurement system device relative to the transmitting device using the rate of change of the first differential distance. | 12-03-2015 |
20150351067 | DISTANCE AND VELOCITY MEASUREMENTS USING CARRIER SIGNALS - Systems and methods for performing distance and velocity measurements, such as by using carrier signals, are disclosed. A measurement method may include transmitting a first signal from an originator device to a transponder device, the first signal having a first carrier frequency; and determining a carrier phase of the first signal at the transponder device. The method may include transmitting a second signal from the transponder device to the originator device, the second signal having a second carrier frequency; and determining a carrier phase of the second signal at the originator device. The method may include estimating a distance between the originator device and the transponder device using the carrier phase of the first carrier signal and the carrier phase of the second carrier signal. The method may include estimating the distance between the originator device and the transponder device using a frequency difference between the first carrier frequency and the second carrier frequency. | 12-03-2015 |
Patent application number | Description | Published |
20090045106 | WATER TREATMENT SYSTEM - A water treatment system (“WTS”) includes a prefilter, a carbon block filter and a microbiological interception (“MI”) filter that operate in combination to treat a fluid stream, such as water. The WTS may include two prefilters, for example, both a multi-layer nonwoven prefilter and a pleated fabric prefilter. The MI filter may include carbon particles and a binder, and the carbon particles may have a mean particle diameter ranging from about 60 microns to about 80 microns and with a particle size distribution in which no more than about 10% by weight of the particles are larger than about 140 mesh and no more than about 10% by weight are smaller than about 500 mesh. In one embodiment, the water treatment system further includes a volumetric end-of-life filter monitor that monitors the life of the MI filter. | 02-19-2009 |
20110050382 | FLUX CONCENTRATOR AND METHOD OF MAKING A MAGNETIC FLUX CONCENTRATOR - A flux concentrator and method for manufacturing a flux concentrator is provided. The method can include combining powdered soft magnetic material, a binder, a solvent, a internal lubricant; mixing the materials to create a mixture, evaporating the solvent from the mixture, molding the mixture to form a flux concentrator, and curing the flux concentrator. The flux concentrator may be laminated and broken into multiple pieces, which makes the flux concentrator more flexible. Breaking the flux concentrator does not significantly affect the magnetic properties. Since the permeability of the binder is very similar to that of air, adding tiny air gaps between the fractions is not significantly different than adding more binder. | 03-03-2011 |
20110303589 | GRAVITY FEED WATER TREATMENT SYSTEM - A portable water treatment system includes at least one sub-system to treat water including a flocculation system, a chlorination system, and a bio-sand filter system. The water treatment system may include multiple sub-systems for treating water that feed into one another. The sand filter system may include a mini bio-sand filter, a foam filter, or a pressed block filter. The flocculation system may include a tank bottom that urges settling particles toward a sump and a ladle that removes settled particles. A manual pump or siphon may be included in the water treatment system. | 12-15-2011 |
20140292101 | SELECTIVE SHIELDING FOR PORTABLE HEATING APPLICATIONS - A wireless power supply and a portable heating device are provided. The wireless power supply includes an electromagnetic shield and the portable heating device includes a magnetic field source. Placement of the magnetic field source proximate the electromagnetic shield can create a local flux window in the electromagnetic shield. The transfer of electromagnetic flux through the local flux window energizes the portable heating device at various locations along the wireless power supply. The effectiveness of the electromagnetic shield is generally maintained away from the flux window, and the electromagnetic shield reduces stray flux that might otherwise damage nearby objects and/or reduce the efficiency of the wireless power supply. | 10-02-2014 |
20140295199 | COMPOSITE METAL SURFACE - A composite metal surface that looks metallic, but permits effective transmission of an electromagnetic field. The composite metal surface can be integrated into various electronic equipment, such as telephones, remote controls, battery doors, keyboards, mice, game controllers, cameras, laptops, inductive power supplies, and essentially any other electronic equipment. The composite metal surface can also be integrated into non-electrically conductive heat sinks, high permeability shielding, and polished metal non-electrically conductive surfaces. | 10-02-2014 |
Patent application number | Description | Published |
20090068807 | DUAL GATE OXIDE DEVICE INTEGRATION - A method of forming devices including forming a first region and a second region in a semiconductor substrate is provided. The method further includes forming a semiconductive material over the first region, wherein the semiconductive material has a different electrical property than the first semiconductor substrate, forming a first dielectric material over the first region, depositing a second dielectric material over the first dielectric material and over the second region, wherein the second dielectric material is different than the first dielectric material, and depositing a gate electrode material over the high dielectric constant material. In one embodiment, the semiconductive material is silicon germanium and the semiconductor substrate is silicon. | 03-12-2009 |
20090325106 | Method for Implant Imaging with Spin-on Hard Masks - A semiconductor fabrication method that includes forming a patterned mask ( | 12-31-2009 |
20130292805 | METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure. | 11-07-2013 |
20130309846 | METHODS OF FORMING A SILICON SEED LAYER AND LAYERS OF SILICON AND SILICON-CONTAINING MATERIAL THEREFROM - Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon. | 11-21-2013 |
20140256064 | METHODS OF REPAIRING DAMAGED INSULATING MATERIALS BY INTRODUCING CARBON INTO THE LAYER OF INSULATING MATERIAL - One illustrative method disclosed herein includes providing a layer of a carbon-containing insulating material having a nominal carbon concentration, performing at least one process operation on the carbon-containing insulating material that results in the formation of a reduced-carbon-concentration region in the layer of carbon-containing insulating material, wherein the reduced-carbon-concentration region has a carbon concentration that is less than the nominal carbon concentration, performing a carbon-introduction process operation to introduce carbon atoms into at least the reduced-carbon-concentration region and thereby define a carbon-enhanced region having a carbon concentration that is greater than the carbon concentration of the reduced-carbon-concentration region and, after introducing the carbon atoms, performing a heating process on at least the carbon-enhanced region. | 09-11-2014 |
20150041906 | METHODS OF FORMING STRESSED FIN CHANNEL STRUCTURES FOR FINFET SEMICONDUCTOR DEVICES - One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches. | 02-12-2015 |
20150044855 | METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure. | 02-12-2015 |
20150060960 | METHODS OF FORMING CONTACT STRUCTURES ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess. | 03-05-2015 |
20150076609 | METHODS OF FORMING STRESSED LAYERS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer. | 03-19-2015 |
20150145071 | METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure. | 05-28-2015 |
20150255555 | METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY DEVICE - One illustrative method disclosed herein involves, among other things, forming a first epi semiconductor material on the exposed opposite sidewalls of a fin to thereby define a semiconductor body, performing at least one etching process to remove at least a portion of the substrate portion of the fin positioned between the first epi semiconductor materials positioned on the opposite sidewalls of the fin and to thereby define a back-gate cavity, forming a back-gate insulating material within the back-gate cavity and on the first epi semiconductor materials, forming a back-gate electrode on the back-gate insulation material within the back-gate cavity and forming a gate structure comprised of a gate insulation layer and a gate electrode around the semiconductor bodies. | 09-10-2015 |
20150279935 | SEMICONDUCTOR DEVICES WITH CONTACT STRUCTURES AND A GATE STRUCTURE POSITIONED IN TRENCHES FORMED IN A LAYER OF MATERIAL - One illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the substrate, a plurality of laterally spaced-apart source/drain trenches formed in the layer of material above the active region, a conductive source/drain contact structure formed within each of the source/drain trenches, a gate trench formed at least partially in the layer of material between the spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure. | 10-01-2015 |
20150279972 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING A LAYER OF MATERIAL HAVING A PLURALITY OF TRENCHES FORMED THEREIN - One method disclosed includes, among other things, forming a plurality of laterally spaced-apart source/drain trenches and a gate trench in a layer of material above an active region, performing at least one process operation through the spaced-apart source/drain trenches to form doped source/drain regions, forming a gate structure within the gate trench, and forming a gate cap layer above the gate structure positioned within the gate trench. | 10-01-2015 |
20150318215 | METHODS FOR REMOVING SELECTED FINS THAT ARE FORMED FOR FINFET SEMICONDUCTOR DEVICES - One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate to thereby define a plurality of fins in the substrate, forming a layer of insulating material in the trenches, performing an etching process sequence to remove at least a portion of one of the plurality of fins and thereby define a fin cavity, wherein the etching process sequence includes performing a first anisotropic etching process and, after performing the first anisotropic etching process, performing a second isotropic etching process. In this embodiment, the method concludes with the step of forming additional insulating material in the fin cavity. | 11-05-2015 |
20150340452 | Buried fin contact structures on FinFET semiconductor devices - A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess. | 11-26-2015 |
20150340457 | METHODS OF FORMING CONDUCTIVE CONTACT STRUCTURES FOR A SEMICONDUCTOR DEVICE WITH A LARGER METAL SILICIDE CONTACT AREA AND THE RESULTING DEVICES - One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material. | 11-26-2015 |
20150340497 | METHODS OF INCREASING SILICIDE TO EPI CONTACT AREAS AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer. | 11-26-2015 |
20150349053 | SEMICONDUCTOR DEVICES WITH A LAYER OF MATERIAL HAVING A PLURALITY OF SOURCE/DRAIN TRENCHES - One device disclosed herein includes an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, first and second laterally spaced-apart source/drain trenches defined in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the first and second laterally spaced-apart source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure. | 12-03-2015 |
20150364378 | FORMING GATE AND SOURCE/DRAIN CONTACT OPENINGS BY PERFORMING A COMMON ETCH PATTERNING PROCESS - One method disclosed herein includes forming an opening in a layer of material so as to expose the source/drain regions of a transistor and a first portion of a gate cap layer positioned above an active region, reducing the thickness of a portion of the gate cap layer positioned above the isolation region, defining separate initial source/drain contacts positioned on opposite sides of the gate structure, performing a common etching process sequence to define a gate contact opening that extends through the reduced-thickness portion of the gate cap layer and a plurality of separate source/drain contact openings in the layer of insulating material, and forming a conductive gate contact structure and conductive source/drain contact structures. | 12-17-2015 |
20160043223 | FINFET SEMICONDUCTOR DEVICES WITH STRESSED LAYERS - A device includes at least one fin defined in a semiconductor substrate, a raised isolation structure surrounding and laterally spaced apart from the fin, and a gate structure extending across and positioned around a first portion of the fin. A buried fin contact structure is positioned inside of the raised isolation structure and extends across, is positioned around, and conductively contacts a second portion of the fin. An upper surface of the buried fin contact structure is positioned level with or below an upper surface of the raised isolation structure. A stress-inducing material layer is positioned on and in contact with the upper surface of the buried fin contact structure, an insulating material layer is positioned above the stress-inducing material layer and the raised isolation structure, and a contact structure extends through at least the insulating and stress-inducing material layers and conductively contacts the buried fin contact structure. | 02-11-2016 |
20160049332 | METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The transistor device includes a gate structure and a gate cap layer positioned above the gate structure. The method includes forming an extended-height epi contact structure that is conductively coupled to the source/drain region. The extended-height epi contact structure includes an upper surface that is positioned at a height level that is above a height level of an upper surface of the gate cap layer. The method further includes performing an etching process to trim at least a lateral width of a portion of the extended-height epi contact structure, and, after performing the etching process, forming a metal silicide material on at least a portion of the trimmed extended-height epi contact structure and forming a conductive contact on the metal silicide material. | 02-18-2016 |