Patent application number | Description | Published |
20080235498 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus for testing a device under test. The test apparatus includes an instruction storing section that stores thereon a test instruction sequence, a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with the executed instruction, a test signal output section that generates a test signal in accordance with the test pattern, and supplies the generated test signal to the device under test, and a result register that stores thereon a value having a predetermined number of bits. Here, the instruction storing section stores thereon the test instruction sequence including therein a result register update instruction to update a value of a designated bit position in the result register with a predetermined value, and when executing the result register update instruction, the pattern generating section updates, with the predetermined value, the value of the bit position in the result register which is designated by the result register update instruction. | 09-25-2008 |
20080235539 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus that tests a device under test. The test apparatus includes a main memory that stores a test instruction stream determining a test sequence for testing the device under test, a sequence cache memory that caches the test instruction stream, a transfer section that reads the test instruction stream stored on the main memory and writes the read stream into the sequence cache memory in accordance with a described sequence, a pattern generating section that sequentially reads and executes instructions from the test instruction stream cached on the sequence cache memory and outputs a test pattern corresponding to the executed instruction, and a test signal output section that generates a test signal according to the test pattern and supplies the generated signal to the device under test, in which the transfer section overwrites the instruction read from the main memory on a space area on the sequence cache memory or an area on which executed instructions are stored and prohibits overwriting the read instruction on an area on which instructions in a predetermined range is stored, the instructions being located in the predetermined range forward from a final instruction among the executed instructions according to the described sequence. | 09-25-2008 |
20080235548 | TEST APPARATUS, AND ELECTRONIC DEVICE - A test apparatus is provided. The test apparatus includes: a main memory that stores pattern data including at least one pattern bit defining a test signal provided to each of a plurality of terminals of the device under test; a pattern cache memory that caches the pattern data read from the main memory; a pattern generation control section that reads pattern data from the main memory and writes the same to the pattern cache memory; a pattern generating section that sequentially reads the pattern data stored in each cache entry of the pattern cache memory and outputs the same; and a channel circuit that generates a test signal corresponding to each of the plurality of terminals based on the pattern data outputted from the pattern generating section and provides the same to the device under test. | 09-25-2008 |
20080235549 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus that tests a device under test. The test apparatus includes a pattern memory that stores a test instruction stream determining a test sequence for testing the device under test, an interval register that stores a repeated interval in response to the fact that the repeated interval showing at least one instruction to be repeatedly executed in the test instruction stream has been specified, an instruction cache that caches the test instruction stream read from the pattern memory, a memory control section that reads the test instruction stream from the pattern memory and writes the read stream into the instruction cache, a pattern generating section that sequentially reads and executes instructions included in the test instruction stream from the instruction cache and generates a test pattern corresponding to the executed instruction, and a signal output section that generates a test signal based on the test pattern and supplies the generated signal to the device under test. The pattern generating section repeatedly executes an instruction stream within the repeated interval in the test instruction stream when the repeated interval is stored on the interval register. | 09-25-2008 |
20080235550 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus for testing a device under test. The test apparatus includes a main instruction storing section that stores thereon a main test instruction sequence, a sub instruction storing section that stores thereon a sub test instruction sequence which is executed when a subroutine call instruction included in the main test instruction sequence is executed, a pattern generating section that (i) sequentially reads and executes an instruction from the main test instruction sequence and outputs (I) a test pattern associated with the executed instruction and (II) timing set information designating a combination of timings for output of the test pattern, (ii) under a condition of executing the subroutine call instruction, sequentially reads and executes an instruction from the sub test instruction sequence designated by the executed subroutine call instruction and outputs (1) a test pattern associated with the executed instruction and (2) timing set information for a test pattern associated with the subroutine call instruction or an instruction which precedes the subroutine call instruction in the main test instruction sequence, and a test signal output section that generates a test signal in accordance with the test pattern, and supplies the test signal to the device under test at a timing designated by the timing set information. | 09-25-2008 |
20080250291 | TEST APPARATUS AND ELECTRONIC DEVICE - A test apparatus that tests a device under test is provided. | 10-09-2008 |
20080258749 | TEST APPARATUS, AND ELECTRONIC DEVICE - A test apparatus that tests a device under test is provided. The test apparatus includes: a main memory that stores a test data row for testing the device under test; a cache memory that caches the test data row read from the main memory; a pattern generation control section that reads each test data which is not aligned in units of word being a data transfer unit of the main memory and writes the same to cache entries different from each other in the cache memory for each test data; and a pattern generating section that sequentially reads the test data stored of each cache entry in the cache memory and generates a test pattern for testing the device under test. | 10-23-2008 |
Patent application number | Description | Published |
20110161763 | TEST APPARATUS AND SYNCHRONIZATION METHOD - Provided is a test apparatus that tests a device under test, comprising (i) a master domain that includes a master period signal generating section, which generates a master period signal, and that operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, and that operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is being held, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is being held. | 06-30-2011 |
20110199133 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus and a test method for substantially synchronizing phases of test signals for each of a plurality of clock domains. The test apparatus tests a device under test including a plurality of clock domains. The test apparatus comprises a period generator that generates a rate signal for determining a test period corresponding to an operation period of the device under test; a pattern generator that generates a test pattern; phase comparing sections that, for each clock domain, receive an operation clock signal of the clock domain acquired from a terminal of the device under test included in the clock domain, and detect a phase difference of the operation clock signal of the clock domain with respect to the rate signal; and a plurality of waveform shaping sections that are provided respectively to the clock domains, and that each shape a test signal based on the test pattern, according to the phase difference of the corresponding clock domain, to substantially synchronize the test signal with the operation clock signal of the corresponding clock domain. | 08-18-2011 |
20110248734 | ELECTRONIC DEVICE TEST APPARATUS - An electronic device test apparatus which can optimize throughput and costs is provided. | 10-13-2011 |
Patent application number | Description | Published |
20140186763 | LIQUID DEVELOPER - A liquid developer containing toner particles containing a resin and a pigment, and an insulating liquid, the toner particles being dispersed in the insulating liquid, wherein the insulating liquid contains an olefin having 12 carbon atoms or more and 18 carbon atoms or less in an amount of 10% by mass or more. The liquid developer of the present invention can be suitably used in developing latent images formed in, for example, an electrophotographic method, an electrostatic recording method, an electrostatic printing method, or the like. | 07-03-2014 |
20140186764 | METHOD FOR PRODUCING LIQUID DEVELOPER - A method for producing a liquid developer containing toner particles containing a resin containing a polyester and a pigment, and an insulating liquid, wherein the toner particles are dispersed in the insulating liquid, including: step 1: melt-kneading the resin and the pigment, and pulverizing a melt-kneaded mixture to provide toner particles; step 2: dispersing the toner particles obtained in the step 1 in the insulating liquid in the presence of a basic dispersant to provide a dispersion of toner particles; and step 3: wet-milling the dispersion of toner particles obtained in the step 2 to provide a liquid developer, wherein the basic dispersant is an amide compound obtained by a reaction between a polyethyleneimine and a polyester (D) obtained by self-condensation of 12-hydroxystearic acid. The liquid developer obtained by the method of the present invention can be suitably used in development of latent images formed in, for example, an electrophotographic method, an electrostatic recording method, an electrostatic printing method, or the like. | 07-03-2014 |