Patent application number | Description | Published |
20080282249 | METHOD AND SYSTEM FOR PERFORMING REAL-TIME OPERATION - An information processing system performs a real-time operation including a combination of a plurality of tasks. The system includes a plurality of processors, a unit which stores structural description information and a plurality of programs describing procedures corresponding to the tasks, the structural description information indicating a relationship in input/output between the programs and including cost information concerning time required for executing each of the programs, a unit which determines an execution start timing and execution term of each of a plurality of threads for execution of the programs based on the structural description information, and a unit which performs a scheduling operation of assigning the threads to at least one of the processors according to a result of the determining. | 11-13-2008 |
20090044188 | METHOD AND SYSTEM FOR PERFORMING REAL-TIME OPERATION - An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio. | 02-12-2009 |
20090319865 | CACHE MEMORY, COMPUTER SYSTEM AND MEMORY ACCESS METHOD - A cache memory has a data holding unit having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal. | 12-24-2009 |
20090319867 | MEMORY SYSTEM AND MEMORY ACCESS METHOD - A memory system has a redundancy coding circuit that performs redundancy coding process for write data, an inverter circuit which inverts values of individual bits of the data that has resulted from the redundancy coding process, a selector which selects the data that has resulted from the redundancy coding process or data that has been inverted by the inverter circuit based on a selecting signal, a memory which stores the selected data, a comparator which compares data read from the memory with the selected data and outputs a comparison result, a write control circuit which generates the selecting signal based on the comparison results, and a redundancy decoding circuit that performs a redundancy decoding process for data read from the memory to output the processed data. | 12-24-2009 |
20100073991 | STORAGE APPARATUS - According to one embodiment, a storage apparatus includes: a first inverter; a second inverter; a first storage element having a first state and a second state; and a second storage element having a third state and a fourth state, wherein the first storage element is brought into the first state when a current flows from the first storage element to the first storage element and is brought into the second state when the current flows from the first storage element to the first storage element, wherein the second storage element is brought into the fourth state when a current flows from the second storage element to the second storage element and is brought into the third state when the current flows from the second storage element to the second storage element. | 03-25-2010 |
20110131366 | MEMORY MANAGEMENT UNIT AND MEMORY MANAGEMENT METHOD - According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory. | 06-02-2011 |
20110276858 | MEMORY SYSTEM - A memory system comprises an encoding processing circuit | 11-10-2011 |
20120026784 | RANDOM NUMBER GENERATOR - According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element comes into a high resistance state corresponding to a first logical value and also comes into a low resistance state corresponding to a second logical value different from the first logical value. The control circuit supplies the MTJ element with a first current for stochastically reversing the MTJ element from the high resistance state to the low resistance state when the MTJ element is in the high resistance state, and supplies the MTJ element with a second current for stochastically reversing the MTJ element from the low resistance state to the high resistance state when the MTJ element is in the low resistance state. | 02-02-2012 |
20120117407 | COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD - According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data. | 05-10-2012 |
20120216003 | SEMICONDUCTOR DEVICE AND MEMORY PROTECTION METHOD - According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets. | 08-23-2012 |
20120246397 | STORAGE DEVICE MANAGEMENT DEVICE AND METHOD FOR MANAGING STORAGE DEVICE - According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor. | 09-27-2012 |
20120311405 | CACHE MEMORY, COMPUTER SYSTEM AND MEMORY ACCESS METHOD - A cache memory has a data holding unit, having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal. | 12-06-2012 |
20130080813 | CONTROL SYSTEM, CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption. | 03-28-2013 |
20140240333 | DATA PROCESSING DEVICE, DISPLAY CONTROL DEVICE, SEMICONDUCTOR CHIP, METHOD OF CONTROLLING DISPLAY DEVICE, AND COMPUTER-READABLE MEDIUM - A data processing device according to embodiments comprises a data converting unit, a selecting unit, a managing unit, a updating unit, and a controller. The data converting unit is configured to convert update-data for updating at least a part of an electronic paper into processed update-data to be displayed. The selecting unit is configured to select an update-control-information identifier to be used for updating the electronic paper with the processed update-data. The managing unit is configured to store the processed update-data and a selected update-control-information identifier on a first memory. The updating unit is configured to instruct a drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored on the first memory. The controller is configured to, when the processed update-data and the update-control-information identifier are stored on the first memory, execute the drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored in the first memory in response to the instruction from the updating unit. | 08-28-2014 |
20140245039 | INFORMATION PROCESSING APPARATUS, DEVICE CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing apparatus includes: a first control unit to control a first device; and a second control unit to control a second device. The first control unit includes a first request processing unit, a notification unit, and a first execution unit. The second request processing unit receives a second request including an instruction to start a process of the second device. The notification unit notifies the second control unit that the first control unit receives a first request. The second execution unit executes a second request received by the second request processing unit when the first device is in the active state, and executes the second request stored in the storage unit when the notification is received by the notification receiving unit. | 08-28-2014 |
20150058588 | SEMICONDUCTOR DEVICE AND MEMORY PROTECTION METHOD - According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets. | 02-26-2015 |
Patent application number | Description | Published |
20080244229 | Information processing apparatus - In an information processing apparatus, a fetch to a storage address of a first storage unit which stores a first instruction executed at first within a plurality of instructions that is included in a software and executed when a processor starts the software via the channel is detected. It is detected that the processor executed a specific instruction within the plurality of instructions via the channel. It is determined whether a predetermined time has passed since the detection of the fetch to the storage address until the detection of the execution of the specific instruction. When it is determined that the predetermined time has not passed, it is determined whether an interrupt to the processor is prohibited based on a result of the processor executing the specific instruction, and an access is released to the process according to a result of determination. | 10-02-2008 |
20080250119 | DATA TRANSFER SCHEME USING CACHING AND DIFFERENTIAL COMPRESSION TECHNIQUES FOR REDUCING NETWORK LOAD - In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices. Even when the name corresponding to the data is not registered so that it is impossible to transfer the corresponding name instead of transferring the data, it is possible to reduce the amount of transfer data among the data transfer devices by transferring the compressed data in which this data is expressed in a compressed form by utilizing the name corresponding to the registered reference data. | 10-09-2008 |
20090164743 | INFORMATION PROCESSING APPARATUS AND DATA RECOVERING METHOD - A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address. | 06-25-2009 |
20090172325 | INFORMATION PROCESSING APPARATUS AND DATA RECOVERING METHOD - In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address. | 07-02-2009 |
20090189686 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER CONTROL METHOD - Each of computing units on a semiconductor integrated circuit includes a first signal output unit that outputs a first status signal indicating a state of a input/output control unit with regard to an access to a storage unit, a second signal output unit that outputs a second status signal indicating a state of a process control unit with regard to an access to a processing unit, and a power control unit that control ON and OFF of power of the storage unit and the processing unit based on states of the first status signal and the second status signal. | 07-30-2009 |
20090222620 | MEMORY DEVICE, INFORMATION PROCESSING APPARATUS, AND ELECTRIC POWER CONTROLLING METHOD - A memory device includes a memory unit that is nonvolatile and is made up of a plurality of memory areas; first retaining units each of which is provided in correspondence with a different one of the memory areas and each of which retains first setting information that defines whether a corresponding one of the memory areas is in an active state or a stop state; and an electric power-source controlling unit that supplies electric power to one or more of the memory areas that correspond to the first setting information defining the memory areas to be in the active state, and stops electric power supply to one or more of the memory areas that correspond to the first setting information defining the memory areas to be in the stop state. | 09-03-2009 |
20090319870 | SEMICONDUCTOR MEMORY DEVICE AND ERROR CORRECTING METHOD - A decoding unit is arranged between a reading unit that reads data with an error correction code added from memory cells on a specific one of the first data lines and an output unit that selectively outputs certain data of the read out data. The decoding unit corrects any errors in the data read out by the reading unit in accordance with the error correction code. The data in which the errors are corrected by the decoding unit is written back in the memory cells on the specific first data line. | 12-24-2009 |
20120246356 | CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied. | 09-27-2012 |
20120246390 | INFORMATION PROCESSING APPARATUS, PROGRAM PRODUCT, AND DATA WRITING METHOD - According to one embodiment, an information processing apparatus includes an auxiliary storage unit, a non-volatile main storage unit, a secondary cell, a first writing unit, and a second writing unit. The non-volatile main storage unit includes a cache area to temporarily store therein data that is to be stored in the auxiliary storage unit. The first writing unit writes the data into the cache area. The second writing unit writes the data written in the cache area into the auxiliary storage unit when an amount of power in the secondary cell is greater than a predetermined first threshold. | 09-27-2012 |
20120246501 | CONTROLLER AND PROGRAM PRODUCT - According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit. | 09-27-2012 |
20120246503 | INFORMATION PROCESSING APPARATUS AND JUDGING METHOD - According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor. | 09-27-2012 |
20130073812 | CACHE MEMORY DEVICE, PROCESSOR, AND INFORMATION PROCESSING APPARATUS - According to an embodiment, a cache memory device caches data stored in or data to be stored in a memory device. The cache memory device includes a memory area that includes a plurality of cache lines; and a controller. When the number of dirty lines among the cache lines exceeds a predetermined number, the controller writes data of the dirty lines into the memory device, each of the dirty lines containing data that is not written in the memory device. | 03-21-2013 |
20130080812 | CONTROL SYSTEM, CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power. | 03-28-2013 |
20130191670 | CONTROL DEVICE, SYSTEM, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs. | 07-25-2013 |
20130254773 | CONTROL APPARATUS, CONTROL METHOD, COMPUTER PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE - According to an embodiment, a control apparatus for controlling a target device includes an estimation unit and an issuing unit. The estimation unit is configured to estimate a second amount of energy required for the entire system including the target device and the control apparatus until the target device completes an execution of its function that is requested in accordance with an execution request for the target device. The issuing unit is configured to issue a control command for causing the target device to execute its function in accordance with the execution request, when the first amount of energy at a time point of receiving the execution request is greater than the second amount of energy. | 09-26-2013 |
20130268781 | STATE CONTROL DEVICE, INFORMATION PROCESSING DEVICE, COMPUTER PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE - According to an embodiment, a state control device controls a state transition of an information processing device. The information processing device includes a processor; a power supply unit; and an electric storage unit. The state control device includes a controller to, when the power amount accumulated in the electric storage unit is decreased to a first power amount while the information processing device is in a first state, cause the information processing device to transit from the first state to a second state in which power consumption of the processor is lower than that in the first state, and to, when the power amount accumulated in the electric storage unit is increased to a second power amount larger than the first power amount while the information processing device is in the second state, cause the information processing device to transit from the second state to the first state. | 10-10-2013 |
20140013138 | MEMORY CONTROL DEVICE, SEMICONDUCTOR DEVICE, AND SYSTEM BOARD - According to an embodiment, a memory control device controls a memory from/to which data are read/written by a processor. The memory control device includes a clock switcher and a control signal switcher. The clock receives as input a first clock and a second clock at a higher frequency than the first clock, supplies the first clock to the memory until the second clock becomes stable, and supplies the second clock after the second clock has become stable. The a control signal switcher starts supplying, to the memory, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor while the first clock is being supplied to the memory, and supplies, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized. | 01-09-2014 |
20140013140 | INFORMATION PROCESSING APPARATUS AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing apparatus includes a processor, a first memory, and a power supply controller. The processor is configured to execute a program. The first memory is configured to store therein the program. The power supply controller is configured to stop supplying a power to the first memory when the processor transitions to an idle state where the processor waits for an interrupt, and start supplying the power to the first memory when the processor receives the interrupt in the idle state. When the processor receives the interrupt in the idle state, the processor executes initialization of the first memory to set the first memory into a state where the first memory is accessible from the processor. | 01-09-2014 |
20140089715 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing apparatus is powered by a power source including a power generation unit and a power storage device that stores power generated by the power generation unit. The information processing apparatus includes a first obtaining, a second obtaining unit, and a first control unit. The first obtaining unit is configured to obtain first information indicating a value of power generated by the power generation unit. The second obtaining unit is configured to obtain second information indicating an value of stored energy in the power storage device. The first control unit is configured to start a process that is set in advance when the value of power indicated by the first information is greater than zero and the value of stored energy indicated by the second information is equal to or greater than a first threshold value. | 03-27-2014 |
20140139500 | CONTROL DEVICE, INFORMATION PROCESSING APPARATUS AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a control device includes a detection unit, a process control unit, and an acquisition unit. The detection unit is configured to detect attachment and detachment of a display device including an electronic paper. The process control unit is configured to write identification information for the display device and process information in association with each other in a storage unit when detachment of the display device is detected. The process information indicates a state of a process for processing content to be displayed on the display device. The acquisition unit is configured to acquire the identification information when attachment of the display device is detected. The process control unit acquires the process information associated with the acquired identification information and causes the process to be in an execution state at a time of detachment of the display device, based on the acquired process information. | 05-22-2014 |
20140245045 | CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a control device includes a processor setting unit, a resumption data reading unit, and a resumption processing unit. The processor setting unit is configured to identify, among a plurality of processors included in an information processing system, each of which is connected to one or more memories, a processor connected to a memory storing resumption data for resuming the information processing system and to activate the identified processor, in response to a resumption request for resuming the information processing system from hibernation. The information processing system includes two or more processors each connected with one or more memories. The resumption data reading unit is configured to read the resumption data from the memory that stores the resumption data. The resumption processing unit is configured to resume the information processing system by using the read resumption data. | 08-28-2014 |
20140245047 | INFORMATION PROCESSING APPARATUS, OPERATION STATE CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing apparatus that includes a processor, has a first control unit, a power storage unit, and a second control unit. The first control unit is configured to control execution of a process by the processor. The power storage unit is configured to store therein power. The second control unit is configured to control reduction of power consumption of the information processing apparatus in a case where there is a process waiting to be executed and an amount of stored power of the power storage unit is equal to or less than a first threshold. | 08-28-2014 |
20150019895 | INFORMATION PROCESSING APPARATUS AND JUDGING METHOD - According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor. | 01-15-2015 |
Patent application number | Description | Published |
20120131418 | MEMORY DEVICE - According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed. | 05-24-2012 |
20120151119 | VIRTUAL MEMORY MANAGEMENT APPARATUS - A virtual memory management apparatus of an embodiment is embedded in a computing machine | 06-14-2012 |
20130219203 | CONTROL DEVICE, CONTROL METHOD, COMPUTER PROGRAM PRODUCT, AND ELECTRONIC DEVICE - According to an embodiment, a power control device includes a storage unit, a monitor, a determining unit, and a controller. The storage device stores a look-up table, which includes relationship between needed power consumptions and start-up conditions of an electronic device including a plurality of modules. The start-up condition of the electronic device is determined from the needed power consumption in the look-up table and specifies a power on/off status of the modules in the electronic device. The monitor monitors a voltage or available power supplied by a power source when the electronic device is activated. The determining unit determines a start-up condition corresponding to needed power consumption, which corresponds to the voltage or available power monitored by the monitor, with reference to the table. The controller sets a start-up condition of the electronic device to start up the electronic device in the start-up condition determined by the determining unit. | 08-22-2013 |
20140075227 | CONTROL DEVICE, DATA PROCESSING DEVICE, CONTROLLER, METHOD OF CONTROLLING THEREOF AND COMPUTER-READABLE MEDIUM - A control device according to embodiments comprises a data-copying unit, a data-processing instructing unit, and a power-control unit. The data-copying unit copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory. The data is to be processed at a first data processing unit. The data-processing instructing unit instructs the first data processing unit to process the data copied to the second memory. The power-control unit switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory. The first power is power supplied to the first memory at a time when the data is copied from the first memory to the second memory. The second power is lower than the first power. | 03-13-2014 |
20140077604 | POWER SUPPLY SYSTEM AND POWER SUPPLY CONTROLLER - According to an embodiment, a power supply system includes a power storage unit, a changeover unit, and a control unit. The power storage unit is configured to store electric power generated by a power generation unit. The changeover unit is configured to make a changeover between a first state in which a load is connected to the power generation unit and a second state in which the load is connected to the power storage unit but not the power generation unit. The control unit is configured to perform control to make the changeover to the first state when a value obtained by subtracting a first value from a value of the electric power fed from the power generation unit is not less than a value of the electric power fed to the load. Otherwise, the control unit is configured to perform control to make the changeover to the second state. | 03-20-2014 |
20140244916 | VIRTUAL MEMORY MANAGEMENT APPARATUS - A virtual memory management apparatus of an embodiment is embedded in a computing machine | 08-28-2014 |