Patent application number | Description | Published |
20120059971 | METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOAD FORWARDING - The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load. | 03-08-2012 |
20120096226 | TWO LEVEL REPLACEMENT SCHEME OPTIMIZES FOR PERFORMANCE, POWER, AND AREA - A two-level replacement scheme is provided for selecting an entry in a cache memory to replace when a cache miss takes place and the memory is full. The scheme divides the tags associated with each memory location of the cache into two or more groups, each group relating to a subset of memory locations of the cache. The scheme uses a first algorithm to select one of the groups and passes the tags for the group through a second algorithm. The second algorithm produces a local index which, when combined with a group index, produces a replacement index that identifies a memory location in the cache to replace. | 04-19-2012 |
20130311724 | CACHE SYSTEM WITH BIASED CACHE LINE REPLACEMENT POLICY AND METHOD THEREFOR - A cache system includes plurality of first caches at a first level of a cache hierarchy and a second cache at a second level of the cache hierarchy which is lower than the first level of cache hierarchy coupled to each of the plurality of first caches. The second cache enforces a cache line replacement policy in which the second cache selects a cache line for replacement based in part on whether the cache line is present in any of the plurality of first caches and in part on another factor. | 11-21-2013 |
20130346694 | PROBE FILTER FOR SHARED CACHES - The claimed subject matter provides a method and apparatus for filtering probes to shared caches. One embodiment of the method includes filtering a probe of one or more of a plurality of first caches based on a plurality of first bits associated with a line indicated by the probe. Each of the plurality of first bits is associated with a different subset of the plurality of first caches and each first bit indicates whether the line is resident in a corresponding subset of the plurality of first caches. A second bit indicates whether the line is resident in more than one of the plurality of first caches in at least one of the subsets of the plurality of first caches. | 12-26-2013 |
20140129776 | STORE REPLAY POLICY - A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided. | 05-08-2014 |
20140189245 | MERGING EVICTION AND FILL BUFFERS FOR CACHE LINE TRANSACTIONS - A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer. | 07-03-2014 |
20140310506 | ALLOCATING STORE QUEUE ENTRIES TO STORE INSTRUCTIONS FOR EARLY STORE-TO-LOAD FORWARDING - The present invention provides a method and apparatus for allocating store queue entries to store instructions for early store-to-load forwarding. Some embodiments of the method include allocating an entry in a store queue to a store instruction in response to the store instruction being dispatched and prior to receiving a translation of a virtual address to a physical address associated with the store instruction. The entry includes storage for data to be written to the physical address by the store instruction. | 10-16-2014 |
20140317356 | MERGING DEMAND LOAD REQUESTS WITH PREFETCH LOAD REQUESTS - A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit. | 10-23-2014 |
20140317357 | PROMOTING TRANSACTIONS HITTING CRITICAL BEAT OF CACHE LINE LOAD REQUESTS - A processor includes a cache memory, a first core including an instruction execution unit, and a memory bus coupling the cache memory to the first core. The memory bus is operable to receive a first portion of a cache line of data for the cache memory, the first core is operable to identify a plurality of data requests targeting the cache line and the first portion and select one of the identified plurality of data requests for execution, and the memory bus is operable to forward the first portion to the instruction execution unit and to the cache memory in parallel. | 10-23-2014 |