Tanzawa, JP
Fumie Tanzawa, Tokyo JP
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20120149902 | PYRROLO[2,3-D]PYRIMIDINE DERIVATIVE - Provided is a compound represented by the Formula (I) having a HER2 inhibitory action or a pharmacologically acceptable salt thereof, | 06-14-2012 |
Fumiko Tanzawa, Tokyo JP
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20110305793 | METHOD OF PRODUCING 3-MERCAPTOHEXAN-1-OL AND ALCOHOL CONTAINING SOLUTION - The present invention relates to a method of production of a solution containing an abundance of 3-mercaptohexan-1-ol (3MH) and alcohol and having a desirable aroma by employing a grape skin extract; an aromatic agent employing the 3MH and alcohol containing solution; a method of production of a drink with an enhanced aroma; and a method of production of fruit liquor, employing a grape skin extract. The method of production of the 3MH and alcohol containing comprising: inoculating a starting material aqueous solution comprising S-(3-hexan-1-ol)glutathione and S-(3-hexan-1-ol)-L-cysteine with a lactic acid bacterium and yeast to produce 3-mercaptohexan-1-ol and alcohol. The starting material aqueous solution comprises a grape skin extract. The lactic acid bacterium is a lactic acid bacterium that is capable of converting S-(3-hexan-1-ol)glutathione to S-(3-hexan-1-ol)-L-cysteine. After inoculating the starting material aqueous solution with a lactic acid bacterium and conducting fermentation for 0 to 6 days, the aqueous solution is inoculated with the yeast and alcohol fermentation is conducted. | 12-15-2011 |
Hideki Tanzawa, Chiba JP
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20080233556 | CYTOTONIC PROTEIN AND UTLIZATION THEREOF - This invention relates to a new cytotoxic protein (M toxin, mucous layer devastating toxin) produced by | 09-25-2008 |
20090208972 | CYTOTOXIC PROTEIN AND UTLIZATION THEREOF - This invention relates to a new cytotoxic protein (M toxin, mucous layer devastating toxin) produced by | 08-20-2009 |
20130288914 | Method Of Determining Administration Effect In Cancer Chemotherapy With S-1 - Provided is a method of determining a therapeutic effect of cancer chemotherapy with an anticancer drug obtained by blending three ingredients, i.e., tegafur, gimeracil, and oteracil potassium as active ingredients (hereinafter abbreviated as S-1) quickly, simply, and accurately before carrying out the cancer chemotherapy. Specifically, provided is a method of determining an administration effect in chemotherapy with S-1, the method comprising: a step (a) of measuring expression level of a decorin gene in a biological sample collected from a subject to be diagnosed; and a step (b) of determining an administration effect of S-1 based on the expression level of the gene obtained from the measurement. | 10-31-2013 |
Masaki Tanzawa, Miyoshi-Shi JP
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20120314225 | BEAD INSPECTION METHOD, AND BEAD INSPECTION APPARATUS - A bead inspection step and a bead inspection apparatus that inspect the quality of a bead are disclosed . . . . The bead inspection apparatus includes a wire-feed-speed measurement device that measures the feed speed of a brazing wire, and an analysis portion that measures and analyzes position coordinate data about surfaces of a first, workpiece, a second workpiece and the bead, and performs a first shape data measurement step of. measuring first shape data before brazing, a second shape data measurement step of measuring second shape data after the brazing, a feature quantity calculation step of calculating predicted values of feature quantities based on the first and second shape data and the brazing wire feed speed, and a throat thickness calculation step of calculating a predicted value of the throat thickness by a regression expression formed based on actual measurements of the feature quantities and of the throat thickness. | 12-13-2012 |
Masaki Tanzawa, Aichi JP
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20090159579 | Butt Welding System of Steel Plate and Butt Welding Method of Steel Plate - A butt welding system and a butt welding method of steel plate by which the quality of a product can be ensured. Butting portions of blank members ( | 06-25-2009 |
Masaki Tanzawa, Toyota-Shi JP
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20100200554 | WELDING EQUIPMENT AND WELDING METHOD - Welding equipment includes a torch for irradiating a laser beam, wire feeding means for feeding a filler wire, and tracking means for controlling the moving tracks of the torch and the wire feeding means so as to make the moving tracks follow a welding line. The tracking means has a contactor provided so as to be advanceable/retractable for making contact with a joint object resiliently. The torch and the wire feeding means are moved so as to follow the welding line by touching the contactor of the tracking means resiliently to the joint object while feeding the filler wire to a welding portion and irradiating that portion with the laser beam, thereby joining the joint objects. | 08-12-2010 |
Naoyori Tanzawa, Kariya-City JP
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20120004908 | VOICE RECOGNITION TERMINAL - A voice recognition terminal executes a local voice recognition process and utilizes an external center voice recognition process. The terminal includes: a voice message synthesizing element for synthesizing at least one of a voice message to be output from a speaker according to the external center voice recognition process and a voice message to be output from the speaker according to the local voice recognition process so as to distinguish between characteristics of the voice message to be output from the speaker according to the external center voice recognition process and characteristics of the voice message to be output from the speaker according to the local voice recognition process; and a voice output element for outputting a synthesized voice message from the speaker. | 01-05-2012 |
Sadamitsu Tanzawa, Ibaraki-Ken JP
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20090056540 | APPARATUS AND METHOD FOR SEPARATING GAS - An apparatus and a method for separating a specified gas from a gas to be treated containing the specified gas comprising at least one ingredient, which comprises allowing the gas to be treated to flow through a column without the use of another gas for transferring the gas to be treated, while keeping the inside of the column packed with a packing material at a reduced pressure. The above apparatus and method can be suitably used for separating a specified gas having a high purity at a low cost. | 03-05-2009 |
Sadamitsu Tanzawa, Naka-Shi JP
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20090056552 | APPARATUS AND METHOD FOR SEPARATING GAS - There is provided a gas separation apparatus for separating a specified gas from a gas to be treated containing a plurality of gases. The gas separation apparatus includes a plurality of serially-connected separation units that separate the specified gas from other gases by using a column, and a suction unit that controls an inside of the column to a reduced pressure. At least two of the plurality of separation units differ from each other in at least one separation condition. | 03-05-2009 |
Toru Tanzawa, Adachi JP
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20140198586 | DEVICES AND SYSTEMS INCLUDING ENABLING CIRCUITS - Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits. | 07-17-2014 |
20140204677 | APPARATUSES AND METHODS INCLUDING MEMORY WRITE OPERATION - Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line. The first access line can be adjacent to the second access line. The memory cells include a memory cell associated with the second access line. A module can be configured to apply a voltage to the first access line during an operation of accessing the memory cell associated with the second access line, and to place the second access line in a floating state during at least a portion of a time interval within the operation. Other embodiments including additional apparatus and methods are described. | 07-24-2014 |
20140321188 | MEMORY DEVICES HAVING DATA LINES INCLUDED IN TOP AND BOTTOM CONDUCTIVE LINES - Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a first set of data lines. At least a portion of the second set of conductive lines is configured as a second set of data lines. Each of the memory strings is coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines. Other embodiments including additional apparatuses and methods are described. | 10-30-2014 |
20140334219 | APPARATUSES AND METHODS INCLUDING MEMORY WITH TOP AND BOTTOM DATA LINES - Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described. | 11-13-2014 |
20140347926 | VERTICAL MEMORY WITH BODY CONNECTION - An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection to the body semiconductor. | 11-27-2014 |
20140355352 | MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE - Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described. | 12-04-2014 |
20150021609 | SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS - Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments. | 01-22-2015 |
20150023104 | APPARATUSES AND METHODS FOR MEASURING AN ELECTRICAL CHARACTERISTIC OF A MODEL SIGNAL LINE AND PROVIDING MEASUREMENT INFORMATION - Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line. | 01-22-2015 |
20150063022 | APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS - Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described. | 03-05-2015 |
Toru Tanzawa, Ebina-Shi JP
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20080205154 | Semiconductor Memory Device - A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline. | 08-28-2008 |
20090164712 | FLASH MEMORY - A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal. | 06-25-2009 |
20100110790 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline. | 05-06-2010 |
20110167320 | FLASH MEMORY - A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal. | 07-07-2011 |
20110222343 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline. | 09-15-2011 |
20130097473 | FLASH MEMORY - A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal. | 04-18-2013 |
Yuichi Tanzawa, Tokyo JP
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20120322557 | VIDEO GAME PROCESSING APPARATUS AND VIDEO GAME PROCESSING PROGRAM - A video game processing apparatus for controlling progress of a video game by displaying an object on a display screen of a display device is provided. The video game processing apparatus includes a plurality of touch panels respectively provided on a plurality of surfaces of all of surfaces on a housing of the video game processing apparatus. The video game processing apparatus receives a touch operation for any one of the plurality of touch panels, and determines which surface of the housing contains the touch panel for which the touch operation is received. The video game processing apparatus carries out a predetermined representation against the object displayed on the display screen from a side of the determined surface. The predetermined representation includes a representation indicating an attack against the object from the side of the determined surface. | 12-20-2012 |
20140018174 | VIDEO GAME PROCESSING APPARATUS AND VIDEO GAME PROCESSING PROGRAM - A video game processing apparatus for controlling progress of a video game by displaying an object on a display screen of a display device is provided. The video game processing apparatus includes a plurality of touch panels respectively provided on a plurality of surfaces of all of surfaces on a housing of the video game processing apparatus. The video game processing apparatus receives a touch operation for any one of the plurality of touch panels, and determines which surface of the housing contains the touch panel for which the touch operation is received. The video game processing apparatus carries out a predetermined representation against the object displayed on the display screen from a side of the determined surface. The predetermined representation includes a representation indicating an attack against the object from the side of the determined surface. | 01-16-2014 |
Yuuichi Tanzawa, Tokyo JP
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20130207909 | SCROLLING SCREEN APPARATUS, METHOD FOR SCROLLING SCREEN, AND GAME APPARATUS - [Problem] The present invention intends to provide a scrolling screen apparatus, a method for scrolling screen, and a game apparatus, which prevent from scrolling display screen by user's misoperation and scroll display screen with intuitive operation. | 08-15-2013 |
Yuuichi Tanzawa, Shinjuku-Ku JP
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20130316817 | INFORMATION PROCESSING APPARATUS, METHOD FOR INFORMATION PROCESSING, AND GAME APPARATUS - User's error operation is prevented by effectively distinguishing an inputting operation of specifying an area on a display screen from a touching or click inputting operation of specifying one point and an operation of sliding an input of one point while continuing inputting the point. The present invention determines a coordinate of a first intermediate point calculated from coordinates of first two points based on the coordinates of the first two points simultaneously inputted to a coordinate input unit, and determines a coordinate of a second intermediate point calculated from coordinates of last two points based on the coordinates of the last two points detected immediately before the coordinates of the two points stop being simultaneously inputted. Further, the present invention defines an area on a display screen of a display unit based on the coordinate of the first intermediate point and the coordinate of the second intermediate point. | 11-28-2013 |
20130331182 | GAME APPARATUS AND GAME PROGRAM - A task of the present invention is to prevent timings of a plurality of objects to arrive at the same destination from becoming uncoordinated and perform efficient computation processing to perform control of moving a plurality of objects in game space to the same destination. A movement control unit of the present invention reads information related to a moving speed of each player object from an object memory unit to perform control of moving a plurality of plurality objects. Further, the movement control unit determines a party moving speed for moving a plurality of player objects as a party based on the read information related to the plurality of moving speeds. Furthermore, the movement control unit performs control of moving a plurality of player objects according to the party moving speed. | 12-12-2013 |