Patent application number | Description | Published |
20160022492 | Systems and Methods for Laser Beam Direct Measurement and Error Budget - Embodiments of the present invention generally describe systems, devices, and methods for directly measuring pulse profiles during pulse delivery. In some embodiment, the pulse profiles may be measured while the pulse is delivered to ablate a material. Embodiments, may calculate ablation spot parameters based on the pulse profiles and may refine one or more subsequent laser pulses based on deviations from the calculated ablation spot parameters from desired ablation spot parameters. In some embodiments, a fluence profiler is provided. The fluence profiler may measure a pulse profile of a laser pulse from a portion of the laser pulse. The fluence profiler may utilize a UV radiation energy sensor device and a camera-based imager. The measurements from the UV radiation energy sensor device and the camera-based imager may be combined and scaled to provide a measured pulse profile that corresponds to the delivered pulse. | 01-28-2016 |
20160025555 | Systems, Devices, and Methods for Calibration of Beam Profilers - Embodiments generally describe systems, devices, and methods for focusing and calibrating beam profilers. A test object is provided that may include an internal housing rotatable within an external housing. The internal housing may house a light source, a collimator, a filter, and/or a diffuser. A plate may be mounted to the internal housing and may include a plurality of markings. In some embodiments, to focus a beam profiler, the test object may be positioned adjacent the converter plate of a beam profiler. Marker images may be captured and a focus quality may be assessed therefrom. A position of the converter, objective, and/or camera of the beam profiler may be adjusted based on the focus quality. To calibrate, images of the markings in several rotational positions may be captured and used for calibration. The markings may be rotated to several positions by rotating the internal housing relative to the external housing. | 01-28-2016 |
Patent application number | Description | Published |
20090213274 | Digital Television Signal Reception - Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly ( | 08-27-2009 |
20100321271 | System and Apparatus for Receiving Digital Television Signals - Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly coupled to the signal processing circuitry and comprising a first antenna positioned to maximize reception in a first direction and a second antenna positioned to maximize reception in a second direction, different from the first direction, and a processor coupled to the antenna assembly and comprising a selection logic module to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module to configure the antenna assembly to receive a signal via a selected antenna. | 12-23-2010 |
20120092561 | System and Apparatus for Receiving Digital Television Signals - Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly coupled to the signal processing circuitry and comprising a first antenna positioned to maximize reception in a first direction and a second antenna positioned to maximize reception in a second direction, different from the first direction, and a processor coupled to the antenna assembly and comprising a selection logic module to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module to configure the antenna assembly to receive a signal via a selected antenna. | 04-19-2012 |
Patent application number | Description | Published |
20080230092 | METHOD AND APPARATUS FOR SINGLE-SUBSTRATE CLEANING - A single-substrate cleaning apparatus and method of use are described. In an embodiment of the present invention, a liquid cleaning solution is dispensed in small volumes to form a substantially uniform static liquid layer over a substrate surface by atomizing the viscous liquid with an inert gas in a two-phase nozzle. In another embodiment of the present invention, after a layer of the cleaning solution is formed over the substrate to be cleaned, acoustic energy is applied to the substrate to improve the cleaning efficiency. In a further embodiment, cleaning solution precipitates are avoided by dispensing de-ionized water with a spray nozzle to gradually dilute the cleaning solution prior to dispensing de-ionized water with a stream nozzle. | 09-25-2008 |
20090090381 | Frontside structure damage protected megasonics clean - An apparatus and method for removing contaminants from a workpiece is described. Embodiments of the invention describe placing a workpiece on a holding bracket within a process chamber to hold and rotate the workpiece to be cleaned. A first cleaning fluid is provided to the workpiece non-device side, while a degasified liquid is provided to the workpiece device side during megasonic cleaning. The degasified liquid inhibits cavitation from occurring on and damaging the device side of the workpiece during megasonic cleaning. | 04-09-2009 |
20090241996 | SINGLE WAFER DRYER AND DRYING METHODS - In a first aspect, a module is provided that is adapted to process a wafer. The module includes a processing portion having one or more features such as (1) a rotatable wafer support for rotating an input wafer from a first orientation wherein the wafer is in line with a load port to a second orientation wherein the wafer is in line with an unload port; (2) a catcher adapted to contact and travel passively with a wafer as it is unloaded from the processing portion; (3) an enclosed output portion adapted to create a laminar air flow from one side thereof to the other; (4) an output portion having a plurality of wafer receivers; (5) submerged fluid nozzles; and/or (6) drying gas flow deflectors, etc. Other aspects include methods of wafer processing. | 10-01-2009 |
20100006124 | SINGLE WAFER DRYER AND DRYING METHODS - In a first aspect, a module is provided that is adapted to process a wafer. The module includes a processing portion having one or more features such as (1) a rotatable wafer support for rotating an input wafer from a first orientation wherein the wafer is in line with a load port to a second orientation wherein the wafer is in line with an unload port; (2) a catcher adapted to contact and travel passively with a wafer as it is unloaded from the processing portion; (3) an enclosed output portion adapted to create a laminar air flow from one side thereof to the other; (4) an output portion having a plurality of wafer receivers; (5) submerged fluid nozzles; and/or (6) drying gas flow deflectors, etc. Other aspects include methods of wafer processing. | 01-14-2010 |
20110230008 | Method and Apparatus for Silicon Film Deposition - Embodiments of the present invention are directed to apparatus and methods for depositing amorphous and microcrystalline silicon films during the formation of solar cells. Specifically, embodiments of the invention provide for a pre-heated hydrogen-containing gas to be introduced into a processing chamber separately from the silicon-containing gas. A plasma, struck from the heated hydrogen-containing gas, reacts with the silicon-containing gas to produce a silicon film on a substrate. | 09-22-2011 |
20130012030 | METHOD AND APPARATUS FOR REMOTE PLASMA SOURCE ASSISTED SILICON-CONTAINING FILM DEPOSITION - An apparatus and methods for depositing amorphous and microcrystalline silicon films during the formation of solar cells are provided. In one embodiment, a method and apparatus is provided for generating and introducing hydrogen radicals directly into a processing region of a processing chamber for reaction with a silicon-containing precursor for film deposition on a substrate. In one embodiment, the hydrogen radicals are generated by a remote plasma source and directly introduced into the processing region via a line of sight path to minimize the loss of energy by the hydrogen radicals prior to reaching the processing region. | 01-10-2013 |
20130139878 | USE OF A1 BARRIER LAYER TO PRODUCE HIGH HAZE ZNO FILMS ON GLASS SUBSTRATES - Embodiments of the invention provide a method for forming a solar cell including forming a layer comprising alumina on a substrate and forming a transparent conductive layer on the layer comprising alumina. The method may also include forming a transparent conductive seed layer on the layer comprising alumina and forming a transparent conductive bulk layer on the transparent conductive seed layer. Embodiments of the invention also include photovoltaic devices having a substrate, a layer comprising alumina adjacent to the substrate, a zinc oxide-containing transparent conductive seed layer adjacent to the layer comprising alumina, and a zinc oxide-containing transparent conductive bulk layer adjacent the zinc oxide-containing transparent conductive seed layer. | 06-06-2013 |
20140196749 | CRYOGENIC LIQUID CLEANING APPARATUS AND METHODS - A cryogenic cleaning apparatus is disclosed. The cryogenic cleaning apparatus has a source of cryogen, a nozzle coupled to the source of cryogen, the nozzle including a main passage adapted to receive the cryogen, one or more auxiliary gas inlets adapted to supply an auxiliary gas to mix with the cryogen either within the nozzle or at a nozzle exit of the nozzle to produce cryogen droplets, and a heated holder adapted to receive a substrate to be cleaned. Cryogenic cleaning methods adapted to clean substrates are provided, as are numerous other aspects. | 07-17-2014 |
20140323017 | METHODS AND APPARATUS USING ENERGIZED FLUIDS TO CLEAN CHEMICAL MECHANICAL PLANARIZATION POLISHING PADS - Methods adapted to clean a chemical mechanical polishing (CMP) pad are disclosed. The methods include positioning an energized fluid delivery assembly over a CMP polishing pad; rotating the polishing pad on a platen; energizing a fluid within the energized fluid delivery assembly; applying the energized fluid to the polishing pad to dislodge slurry residue and debris; and removing the dislodged slurry residue and debris using a vacuum suction unit. Systems and apparatus for carrying out the methods are provided, as are numerous additional aspects. | 10-30-2014 |
20140329439 | APPARATUS AND METHODS FOR ACOUSTICAL MONITORING AND CONTROL OF THROUGH-SILICON-VIA REVEAL PROCESSING - A TSV (through silicon via) reveal process using CMP (chemical mechanical polishing) may be acoustically monitored and controlled to detect TSV breakage and automatically respond thereto. Acoustic emissions received by one or more acoustic sensors positioned proximate a substrate holder and/or a polishing pad of a CMP system may be analyzed to detect TSV breakage during a CMP process. In response to detecting TSV breakage, one or more remedial actions may automatically occur. In some embodiments, a polishing pad platen may have one or more acoustic sensors integrated therein that extend into a polishing pad mounted on the polishing pad platen. Methods of monitoring and controlling a TSV reveal process are also provided, as are other aspects. | 11-06-2014 |
20150114430 | SYSTEMS, METHODS AND APPARATUS FOR POST-CHEMICAL MECHANICAL PLANARIZATION SUBSTRATE BUFF PRE-CLEANING - In some embodiments, an apparatus for cleaning a substrate is provided that includes (1) a substrate chuck configured to support a substrate with a front side of the substrate accessible; (2) a buff pad assembly configured to support a buff pad having a diameter smaller than a diameter of the substrate; and (3) a swing arm coupled to the buff pad and configured to position and rotate the buff pad along the front side of the substrate, and control an amount of force applied by the buff pad against the front side of the substrate during cleaning. The substrate chuck, buff pad assembly and swing arm are configured to buff clean the substrate. Numerous additional aspects are disclosed. | 04-30-2015 |
Patent application number | Description | Published |
20090011440 | Receptor Tyrosine Kinase Signaling Pathway Analysis For Diagnosis And Therapy - The invention provides a method for determining the activation status of receptor tyrosine kinase (RTK) pathways in either cell samples or patient samples by measuring receptor dimerization and relative amounts of protein-protein complexes or activated effector proteins that are characteristic of an RTK pathway. The invention also provides a method of using such status information to select patients responsive to pathway-specific drugs, and more particularly, to methods for measuring ErbB receptors and receptor complexes and using such information to select patients responsive to ErbB pathway-specific drugs. Preferably, methods of the invention are implemented by using sets of binding compounds having releasable molecular tags that are specific for multiple components of one or more complexes formed in RTK activation. After binding, molecular tags are released and separated from the assay mixture for analysis. | 01-08-2009 |
20120036175 | DETERMINING POPULATION BOUNDARIES USING RADIAL DENSITY HISTOGRAMS - Apparatuses and methods for determining population boundaries are described. In one embodiment, population boundaries are determined using radial density histograms. | 02-09-2012 |
20120245889 | Neighborhood Thresholding in Mixed Model Density Gating - The present invention provides automatic gating methods that are useful to gate populations of interest in multidimensional data, wherein the populations of interest are only a subset of the populations identifiable in the data. The populations are modeled as a finite mixture of multivariate probability distributions, preferably normal or t distributions. The distribution parameters that provide a best fit of the model distribution to the data are estimated using an Expectation Maximization (EM) algorithm that further includes a dynamic neighborhood thresholding that enables gating of a subset of the clusters present in the data. | 09-27-2012 |
20150160115 | NEIGHBORHOOD THRESHOLDING IN MIXED MODEL DENSITY GATING - The present invention provides automatic gating methods that are useful to gate populations of interest in multidimensional data, wherein the populations of interest are only a subset of the populations identifiable in the data. The populations are modeled as a finite mixture of multivariate probability distributions, preferably normal or t distributions. The distribution parameters that provide a best fit of the model distribution to the data are estimated using an Expectation Maximization (EM) algorithm that further includes a dynamic neighborhood thresholding that enables gating of a subset of the clusters present in the data. | 06-11-2015 |
Patent application number | Description | Published |
20090018988 | METHOD AND SYSTEM FOR CREATING SEMANTIC RELATIONSHIPS USING HYPERLINKS - A method and system are disclosed for creating a hyperlink together with an associated semantic link between a source entity, and a target entity. The source entity includes descriptive text. The system includes means for selecting text within the source entity, and means for selecting the target entity. Also, means are provided for selecting a type of semantic link, and means are provided for creating a hyperlink between said selected text and said target entity. The system further includes means for creating a semantic link of said type between said source entity and said target entity, including means for including in the hyperlink a reference to said semantic link. In the preferred embodiment of the invention, the means for selecting the type of semantic link includes means for prompting a user to select from among a plurality of candidate types of semantic links. | 01-15-2009 |
20090019353 | MANIPULATING DESIGN MODELS BY EDITING GENERATED REPORTS - A method and system are disclosed for manipulating a model, where that model represents some or all of a design. The design includes a multitude of design elements, the model includes a multitude of model elements, and each of the design elements is represented by a single model element. The method comprises the steps of generating a suite of documents from the model, each of the documents describing a view of the model; and displaying the documents to a user as a series of forms. The user provides information to the forms to change the documents, and changes to the documents result in both changes to the model and consistent changes across the suite of documents. In the preferred embodiment, the model identifies specific relationships between the elements of the model, and each of the model elements has defined properties. | 01-15-2009 |
Patent application number | Description | Published |
20130176775 | FINDING OPTIMAL READ THRESHOLDS AND RELATED VOLTAGES FOR SOLID STATE MEMORY - An expected value associated with stored values in solid state storage, as well as a set of three or more points are obtained where the three or more points include a voltage and a value associated with stored values. Two points having ratios closest to the expected value are selected from the set. A voltage is determined based at least in part on the selected two points and the expected value. | 07-11-2013 |
20130229867 | GENERATING SOFT READ VALUES USING BINS AND/OR MULTIPLE READS - A starting read threshold is received. A first offset and a second offset is determined. A first read is performed at the starting read threshold offset by the first offset to obtain a first hard read value and a second read is performed at the starting read threshold offset by the second offset to obtain a second hard read value. A soft read value is generated based at least in part on the first hard read value and the second hard read value. | 09-05-2013 |
20140013166 | POWER SAVING TECHNIQUES THAT USE A LOWER BOUND ON BIT ERRORS - A read back bit sequence and charge constraint information are obtained. A lower bound on a number of bit errors associated with the read back bit sequence is determined based at least in part on the read back bit sequence and the charge constraint information. The lower bound and an error correction capability threshold associated with an error correction decoder are compared. In the event the lower bound is greater than or equal to the error correction capability threshold, an error correction decoding failure is predicted and in response to the prediction a component is configured to save power. | 01-09-2014 |
20140304480 | NEIGHBOR BASED AND DYNAMIC HOT THRESHOLD BASED HOT DATA IDENTIFICATION - An address is received. One or more neighbors associated with the received address is/are determined. One or more neighboring hot metrics is/are determined for the one or more neighbors associated with the received address. A hot metric for the received address is determined based at least in part on the neighboring hot metrics. | 10-09-2014 |
20150033095 | BUFFER MANAGEMENT IN A TURBO EQUALIZATION SYSTEM - A plurality of partially-decoded codewords that have been processed at least once by a first and a second error correction decoder is stored. A plurality of metrics associated with how close a corresponding partially-decoded codeword is to being successfully decoded is stored. From the plurality of partially-decoded codewords, a codeword having a metric indicating that that codeword is the closest to being successfully decoded by the first error correction decoder and the second error correction decoder is selected. The selected codeword is output to the first error correction decoder. | 01-29-2015 |
20150078084 | GENERATING READ THRESHOLDS USING GRADIENT DESCENT AND WITHOUT SIDE INFORMATION - A first bit position of a cell in solid state storage is read where a sorting bit is obtained using the read of the first bit position. A second bit position of the cell is read for a first time, including by setting a first read threshold associated with the second bit position to a first value and setting a second read threshold associated with the second bit position to a second value. The second bit position of the cell is read for a second time, including by setting the first read threshold to a third value and setting the second read threshold to a fourth value. A new value for the first read threshold and for the second read threshold is generated using the sorting bit, the first read, and the second read. | 03-19-2015 |
20150085572 | STORAGE OF READ THRESHOLDS FOR NAND FLASH STORAGE USING LINEAR APPROXIMATION - A first read threshold associated with a first page in a block and a second read threshold associated with a second page in the block are received, where the first page has a first page number and the second page has a second page number. A slope and a y intercept are determined based at least in part on the first read threshold, the second read threshold, the first page number, and the second page number. The slope and the y intercept are stored with a block identifier associated with the block. | 03-26-2015 |
20150089323 | ERROR RECOVERY USING ERASURES FOR NAND FLASH - Error correction decoding is performed on a codeword where the codeword is unable to be successfully decoded. One or more bits in the codeword are selected to be replaced with an erasure. The selected bits in the codeword is/are replaced with an erasure to obtain a codeword with one or more erasures. Error correction decoding is performed on the codeword with one or more erasures. | 03-26-2015 |
20150131376 | THRESHOLD ESTIMATION USING BIT FLIP COUNTS AND MINIMUMS - A bit flip count is determined for each bin in a plurality of bins, including by: (1) performing a first read on a group of solid state storage cells at a first threshold that corresponds to a lower bound for a given bin and (2) performing a second read on the group of solid state storage cells at a second threshold that corresponds to an upper bound for the given bin. A minimum is determined using the bit flip counts corresponding to the plurality of bins and the minimum is used to estimate an optimal threshold. | 05-14-2015 |
20150138894 | FINDING OPTIMAL READ THRESHOLDS AND RELATED VOLTAGES FOR SOLID STATE MEMORY - A read is performed using a first iteration of a read threshold voltage that is set to a default voltage to obtain a first characteristic. A second iteration of the read threshold voltage is generated using the default voltage and an offset. A read is performed using the second iteration of the read threshold voltage to obtain a second characteristic. A third iteration of the read threshold voltage is generated using the first and second characteristics. A read is performed using the third iteration of the read threshold voltage to obtain a third characteristic. It is determined if the third characteristic is one of the two characteristics closest to a stored characteristic. If so, a fourth iteration of the read threshold voltage is generated using the two closest characteristics. | 05-21-2015 |
20160098350 | SIZING A CACHE WHILE TAKING INTO ACCOUNT A TOTAL BYTES WRITTEN REQUIREMENT - A total bytes written (TBW) requirement associated with solid state storage is obtained. A size of a cache associated with the solid state storage is determined based at least in part on the TBW requirement. The size of the cache is adjusted to be the determined size | 04-07-2016 |
Patent application number | Description | Published |
20100318568 | COMPUTER-IMPLEMENTED METHOD AND SYSTEM FOR COMBINING KEYWORDS INTO LOGICAL CLUSTERS THAT SHARE SIMILAR BEHAVIOR WITH RESPECT TO A CONSIDERED DIMENSION - A computer-implemented method and system for combining keywords into logical clusters that share a similar behavior with respect to a considered dimension are disclosed. Various embodiments are operable to order a list of keywords from high activity to low activity, partition the list into at least two sets, a head partition including keywords with an activity level above a predefined threshold, a tail partition including the remainder of the keywords in the list, model the keywords in the head partition based on a set of variables, score the keywords in the head partition based on the modeling, and cluster head partition keywords with tail partition keywords having at least one common variable into at least one keyword cluster. | 12-16-2010 |
20120016906 | COMPUTER-IMPLEMENTED METHOD AND SYSTEM FOR ENABLING THE AUTOMATED SELECTION OF KEYWORDS FOR RAPID KEYWORD PORTFOLIO EXPANSION - A computer-implemented method and system for enabling the automated selection of keywords for rapid keyword portfolio expansion are disclosed. Various embodiments are operable to normalize a plurality of keywords received from a source, filter the normalized plurality of keywords against one or more keyword filtration lists, produce site-specific variants of the filtered plurality of keywords, associate at least one level of dimension data with each of the plurality of keywords, and store the processed plurality of keywords and dimension data in a keyword database. | 01-19-2012 |
20140164383 | COMPUTER-IMPLEMENTED METHOD AND SYSTEM FOR COMBINING KEYWORDS INTO LOGICAL CLUSTERS THAT SHARE SIMILAR BEHAVIOR WITH RESPECT TO A CONSIDERED DIMENSION - A computer-implemented method and system for combining keywords into logical clusters that share a similar behavior with respect to a considered dimension are disclosed. Various embodiments are operable to order a list of keywords from high activity to low activity, partition the list into at least two sets, a head partition including keywords with an activity level above a predefined threshold, a tail partition including the remainder of the keywords in the list, model the keywords in the head partition based on a set of variables, score the keywords in the head partition based on the modeling, and cluster head partition keywords with tail partition keywords having at least one common variable into at least one keyword cluster. | 06-12-2014 |
20150206184 | COMPUTER-IMPLEMENTED METHOD AND SYSTEM FOR ENABLING THE AUTOMATED SELECTION OF KEYWORDS FOR RAPID KEYWORD PORTFOLIO EXPANSION - A computer-implemented method and system for enabling the automated selection of keywords for rapid keyword portfolio expansion are disclosed. Various embodiments are operable to normalize a plurality of keywords received from a source, filter the normalized plurality of keywords against one or more keyword filtration lists, produce site-specific variants of the filtered plurality of keywords, associate at least one level of dimension data with each of the plurality of keywords, and store the processed plurality of keywords and dimension data in a keyword database. | 07-23-2015 |
Patent application number | Description | Published |
20120267736 | Method And System For Providing A Magnetic Junction Having An Engineered Barrier Layer - A magnetic junction usable in a magnetic memory and a method for providing the magnetic memory are described. The method includes providing a pinned layer, providing an engineered nonmagnetic tunneling barrier layer, and providing a free layer. The pinned layer and the free layer each include at least one ferromagnetic layer. The engineered nonmagnetic tunneling barrier layer has a tuned resistance area product. In some aspects, the step of providing the engineered nonmagnetic tunneling barrier layer further includes radio-frequency depositing a first oxide layer, depositing a metal layer, and oxidizing the metal layer to provide a second oxide. | 10-25-2012 |
20120319221 | METHOD AND SYSTEM FOR PROVIDING A MAGNETIC JUNCTION CONFIGURED FOR PRECESSIONAL SWITCHING USING A BIAS STRUCTURE - A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a first pinned layer having a first pinned layer magnetization, a first nonmagnetic spacer layer, and a free layer having an easy axis. The first nonmagnetic spacer layer is between the first pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction and such that the free layer employs precessional switching. | 12-20-2012 |
20130009260 | Method And System For Providing A Magnetic Junction Using Half Metallic Ferromagnets - A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the free layer and the pinned layer include at least one half-metal. | 01-10-2013 |
20140008742 | MAGNETIC TUNNELING JUNCTION SEED, CAPPING, AND SPACER LAYER MATERIALS - In one embodiment, a magnetic element for a semiconductor device includes a reference layer, a free layer, and a nonmagnetic spacer layer disposed between the reference layer and the free layer. The nonmagnetic spacer layer includes a binary, ternary, or multi-nary alloy oxide material. The binary, ternary, or multi-nary alloy oxide material includes MgO having one or more additional elements selected from the group consisting of: Ru, Al, Ta, Tb, Cu, V, Hf, Zr, W, Ag, Au, Fe, Co, Ni, Nb, Cr, Mo, and Rh. | 01-09-2014 |
20140151829 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTION ELEMENTS HAVING IMPROVED PERFORMANCE THROUGH CAPPING LAYER INDUCED PERPENDICULAR ANISOTROPY AND MEMORIES USING SUCH MAGNETIC ELEMENTS - A magnetic element and a magnetic memory utilizing the magnetic element are described. A contact is electrically coupled to the magnetic element. The magnetic element includes pinned, nonmagnetic spacer, and free layers and a perpendicular capping layer adjoining the free layer and the contact. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy. The free layer is switchable between magnetic states when a write current is passed through the magnetic element. The free layer includes ferromagnetic layers interleaved with capping layer(s) such that a ferromagnetic layer resides at an edge of the free layer. The capping layer(s) are configured such that the ferromagnetic layers are ferromagnetically coupled. | 06-05-2014 |
20140175582 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS HAVING ENGINEERED PERPENDICULAR MAGNETIC ANISOTROPY - A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a reference layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The free layer has an engineered perpendicular magnetic anisotropy. The engineered PMA includes at least one of an insulating insertion layer induced PMA, a stress induced PMA, PMA due to interface symmetry breaking, and a lattice mismatch induced PMA. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 06-26-2014 |
20140264671 | MAGNETIC JUNCTIONS HAVING INSERTION LAYERS AND MAGNETIC MEMORIES USING THE MAGNETIC JUNCTIONS - A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a reference layer, a nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. A portion of the magnetic junction includes at least one magnetic substructure. The magnetic substructure includes at least one Fe layer and at least one nonmagnetic insertion layer. The at least one Fe layer shares at least one interface with the at least one nonmagnetic insertion layer. Each of the at least one nonmagnetic insertion layer consists of at least one of W, I, Hf, Bi, Zn, Mo, Ag, Cd, Os and In. | 09-18-2014 |
20150041933 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS USING BCC COBALT AND SUITABLE FOR USE IN SPIN TRANSFER TORQUE MEMORIES - A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer includes body-centered cubic Co. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 02-12-2015 |
20150129993 | METHOD AND SYSTEM FOR PROVIDING A BULK PERPENDICULAR MAGNETIC ANISOTROPY FREE LAYER IN A PERPENDICULAR MAGNETIC JUNCTION USABLE IN SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS - A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer includes at least one of a hybrid perpendicular magnetic anisotropy (PMA) structure and tetragonal bulk perpendicular magnetic anisotropy (B-PMA) structure. At least one of the free layer and the pinned layer have a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 05-14-2015 |
20150129996 | METHOD AND SYSTEM FOR PROVIDING A TOP PINNED LAYER PERPENDICULAR MAGNETIC ANISOTROPY MAGNETIC JUNCTION USABLE IN SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS - A method for providing a magnetic junction usable in a magnetic device and the magnetic junction are described. A free layer and nonmagnetic spacer layer are provided. The free layer and nonmagnetic spacer layer are annealed at an anneal temperature of at least three hundred fifty degrees Celsius. A pinned layer is provided after the annealing step. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 05-14-2015 |
20150129997 | DUAL PERPENDICULAR MAGNETIC ANISOTROPY MAGNETIC JUNCTION USABLE IN SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS - A method for providing a dual magnetic junction usable in a magnetic device and the dual magnetic junction are described. First and second nonmagnetic spacer layers, a free layer and pinned are provided. The first pinned layer, free layer and nonmagnetic spacer layer may be annealed at an anneal temperature of at least three hundred fifty degrees Celsius before a second pinned layer is provided. The second pinned layer may include Co, Fe and Tb. The nonmagnetic spacer layers are between the pinned layers and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 05-14-2015 |
Patent application number | Description | Published |
20150339318 | OFFLINE BILL SPLITTING SYSTEM - Systems and method for splitting a bill offline include detecting one or more local devices using local wireless communications provided by a peer-to-peer communication module. At least one payer device of the one or more local devices is selected for apportioning a primary bill. An offline payment authorization is then received from each at least one payer device through local wireless communications provided by the peer-to-peer communication module. When an Internet connection is later detected, the system provider connects to the Internet and sends the offline payment authorization received from each at least one payer device to a payment provider device over the Internet. The payment provider device may then transfer funds from account(s) of the at least one payer device to the account of the system provider. | 11-26-2015 |
20150355893 | SYSTEMS AND METHODS FOR LOCATION-BASED APPLICATION INSTALLATION - A system and/or method may be provided to install applications based on location. In particular, a location of a user device may be detected. Based on the location of the user device, one or more applications may be selected to be installed automatically on the user device. Further, when the user device departs from the location, the application may automatically be uninstalled. Thus, applications may be installed and/or uninstalled on the user device based on the location of the user device. The automatically installed application may provide functionality or information associated with the location that triggered the installation. For example, a merchant's store may be associated with the merchant's application which may be installed automatically on devices of customers who enter the merchant's store. | 12-10-2015 |
20160057626 | USING A WIRELESS BEACON TO PROVIDE ACCESS CREDENTIALS TO A SECURE NETWORK - There are provided systems and methods for using a wireless beacon to provide access credentials to a secure network. A network access device, such as a WiFi router, may provide a secure wireless network requiring access credentials to access the network. For example, the network may be password protected to prevent unauthorized used. Additionally, the network may have various levels of use, such as access depending on a security clearance for a user or data transfer and usage rates. Each of the various levels of use may require a separate access credential. A wireless beacon may be configured to connect to user devices that are near or within an area covered by the network. The connection between a user device and the beacon may be utilized to determine the proper access credential for the user device and push the access credential to the user device. | 02-25-2016 |
Patent application number | Description | Published |
20130088925 | LAYOUT OF MEMORY CELLS - A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region. | 04-11-2013 |
20130088926 | TRACKING MECHANISMS - A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro. | 04-11-2013 |
20140032871 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell. | 01-30-2014 |
20140282318 | TIMING DELAY CHARACTERIZATION METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay. | 09-18-2014 |
20140282319 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted. | 09-18-2014 |
20150029797 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line. | 01-29-2015 |
20150071016 | TRACKING MECHANISMS - A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated. | 03-12-2015 |
20150095867 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block. | 04-02-2015 |
20150131391 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal. | 05-14-2015 |
20150162060 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line. | 06-11-2015 |
20150178430 | TIMING DELAY CHARACTERIZATION METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay. The processor is further configured to generate timing delays of the memory circuit based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay. | 06-25-2015 |
20150213858 | READING DATA FROM A MEMORY CELL - In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction. | 07-30-2015 |