| Patent application number | Description | Published |
|---|
| 20080204298 | AD CONVERTER AND RADIO RECEIVER - Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n≦m≦2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position. | 08-28-2008 |
| 20080291070 | DIGITAL/ANALOG CONVERTER AND TRANSMITTER - According to an embodiment of the invention, there is provided a digital/analog converter includes: a decoder that converts a (n−1)-phase input digital signal to a n-phase output digital signal; and a signal generating unit that generates analog signals according to the n-phase output digital signal. | 11-27-2008 |
| 20080315246 | TRANSISTOR SWITCH CIRCUIT AND SAMPLE-AND-HOLD CIRCUIT - A transistor switch circuit includes: a MOS transistor in which a channel is formed when a gate-source voltage is zero; and a voltage supply part which is connected to a gate of the MOS transistor to supply the gate with a voltage for turning off the MOS transistor. | 12-25-2008 |
| 20090045995 | COMPARATOR AND ANALOG-TO-DIGITAL CONVERTER USING THE SAME - A comparator includes a first inverter which is inserted between a power source terminal and one end of a first variable resistor, includes a first FinFET provided with a first gate terminal for receiving a positive phase output signal, and a second gate terminal for receiving a clock signal changing between a first level and a second level, inverts the positive phase output signal, and outputs a negative phase output signal, and a second inverter which is inserted between the power source terminal and one end of a second variable resistor, includes a second FinFET provided with a third gate terminal for receiving the negative phase output signal, a fourth gate terminal for receiving the clock signal, and the same polarity as the first FinFET, inverts the negative phase output signal, and outputs the positive phase output signal. | 02-19-2009 |
| 20090079598 | SAMPLE RATE CONVERTER - The sample rate converter includes a synthesizing unit which synthesizes an input signal sampled with frequency fs with a feedback signal of the frequency fs, in a frequency band from 0 to fs/N (where N indicates a natural number), with a gain greater than at least 1, to generate a synthesized signal, a downsampler which downsamples the synthesized signal to obtain an output signal of sample rate fs/N, and an upsampler which upsamples the output signal to generate the feedback signal. | 03-26-2009 |
| 20090245429 | SAMPLE RATE CONVERTER AND RECEIVER USING THE SAME - A sample rate converter includes a multiplexer which multiplexes input signals, an interpolator which interpolates a multiplexed output signal to generate a first feedback signal, a multiplier which multiplies the first feedback signal by a coefficient, a subtracter which subtracts the multiplied signal from the multiplexed input signal, an adder which adds the residual signal and a second feedback signal to sequentially generate integrated signals corresponding to the input signals, respectively, a register circuit configured to individually hold integrated signals, a multiplexer which multiplexes the integrated signals from the register circuit to generate the second feedback signal, a multiplexer which multiplexes the integrated signals from the register circuit to generate a decimation target signal, a decimator which subjects the decimation target signal to decimation to generate the multiplexed output signal, and a discrimination circuit configured to discriminate the multiplexed output signal to generate output signals. | 10-01-2009 |
| 20090245437 | SAMPLE RATE CONVERTER AND RCEIVER USING THE SAME - A sample rate converter includes a multiplexer to select either one of an input signal and a first feedback signal, and to obtain a selected input signal, a decimator performing decimation on an Nth-order integration signal to generate an output signal, an interpolator performing interpolation on the output signal to generate a second feedback signal, a multiplier which multiplies the second feedback signal by a coefficient to generate a multiplication signal, a subtractor which subtracts the multiplication signal from the selected input signal to generate a residual signal, an adder which adds the residual signal to a third feedback signal to sequentially generate 1st-order to Nth-order integration signals, a register circuit configured to hold the integration signals, a multiplexer to select the first feedback signal from the integration signals that the register hold, and a multiplexer to select the third feedback signal from the integration signals that the register hold. | 10-01-2009 |
| 20090296858 | DEM SYSTEM, DELTA-SIGMA A/D CONVERTER, AND RECEIVER - A DEM (dynamic element matching) system in which a digital signal is inputted, has a switching circuit which, being equipped with a plurality of switches, each of the plurality of switches is subjected to on/off control based on a switch control signal, receives a first thermometer code in which the total number of logic ones and logic zeros corresponding to the digital signal is “n” and outputs a second thermometer code in which the total number of logic ones and logic zeros is “n” (where “n” is an integer equal to or larger than 2), a latch circuit which latches the second thermometer code output from the switching circuit and outputs the second thermometer code, and a switch control signal generating circuit which generates the switch control signal using the digital signal or the second thermometer code output from the latch circuit and outputs the switch control signal. | 12-03-2009 |
