Patent application number | Description | Published |
20090072630 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING ELECTROSTATIC ACTUATOR - A semiconductor device controls an electrostatic actuator having first and second electrodes. A voltage generation unit generates different types of voltages applied to the first and second electrodes. A control unit controls voltages generated by the voltage generation unit to be applied to the first and second electrodes. A capacitance detection unit detects a voltage of the first or second electrode to detect a capacitance between the first and second electrodes. The control unit applies a first voltage between the first and second electrodes and then a second voltage smaller than the first voltage between the first and second electrodes. Thereafter, the control unit switches one of the first electrode or the second electrode to a high impedance state and then changes a voltage applied to the other. The capacitance detection unit detects the amount of change in voltage of the first or second electrode to detect a capacitance between the first and second electrodes. | 03-19-2009 |
20090309640 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING A MASTER-SLAVE FLIP-FLOP - A semiconductor integrated circuit having a flip-flop with improve soft error resistance, including a controller which controls a clock signal generating circuit to output a first clock signal and a second clock signal with a timing so that logic of data retained in a first data retaining terminal becomes identical to logic of data retained in a third data retaining terminal, and then turns on a first switching circuit to connect between the first data retaining terminal and the first data retaining terminal. | 12-17-2009 |
20100039135 | SEMICONDUCTOR INTEGRATED CIRCUIT - Semiconductor integrated circuit has a control circuit. The control circuit causes the clock signal generating circuit to control the first clock signal and the second clock signal to make a logic of data held by the first data holding terminal and a logic of data held by the second data holding terminal equal to each other, and switches on the switch circuit, and the error detection circuit senses a logic of the first data holding terminal and a logic of the second data holding terminal after switching on the switching circuit. | 02-18-2010 |
20100157693 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of binary-data holding memory cells arranged at the intersections of the word lines and the bit lines; and a control unit operative to change in the storage capacity of the memory cell array and change in the address space required for access to the memory cell based on a control signal. | 06-24-2010 |
20120316291 | BLOCK POLYISOCYANATE COMPOSITION AND COATING COMPOSITION CONTAINING SAME - Provided is a block polyisocyanate composition comprising at least one block polyisocyanate represented by formula (I): R-(A) | 12-13-2012 |
20130106318 | SEMICONDUCTOR DEVICE AND DRIVE METHOD OF ELECTROSTATIC ACTUATOR | 05-02-2013 |
20130154606 | POWER CIRCUIT - According to one embodiment, there is provided a power circuit including a DC/DC converter, an A/D converter, a control unit, a determining unit, and a conversion timing adjusting unit. The determining unit determines whether a transition timing of the conversion candidate timing signal overlaps a transition timing of the first switching signal or a transition timing of the second switching signal. The conversion timing adjusting unit adjusts the conversion candidate timing signal so that the transition timing of the conversion candidate timing signal does not overlap the transition timing of the first switching signal and the transition timing of the second switching signal when the transition timing of the conversion candidate timing signal overlaps the transition timing of the first switching signal or the transition timing of the second switching signal to thereby generate the conversion timing signal. | 06-20-2013 |
20130303258 | IMAGE PROCESSOR AND METHOD THEREFOR - By rendering lower half of 30 FPS in the processing of even numbered frame of 60 fps and rendering upper half of 30 fps in the processing of odd numbered frame, the processing load of the processor | 11-14-2013 |
20140028270 | SYNCHRONOUS RECTIFICATION TYPE POWER CIRCUIT AND METHOD OF ADJUSTING THE SAME - According to one embodiment, a synchronous rectification type power circuit includes a first power terminal to which a voltage on a high potential side is supplied, a second power terminal to which a voltage on a low potential side is supplied, an output terminal that outputs an output voltage to a load having an inductance and a capacitor, a first switch unit connected between the first power terminal and the output terminal, a second switch unit connected between the second power terminal and the output terminal, a control signal generating circuit which controls ON/OFF of the first and second switch units, and a control circuit that compares the output voltage with a predetermined reference voltage for a predetermined period when the second switch unit is turned OFF. A timing for turning OFF the second switch unit is adjusted based on a result of the comparison. | 01-30-2014 |
20140268999 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value. | 09-18-2014 |