Patent application number | Description | Published |
20090300410 | SEMICONDUCTOR INTEGRATED CIRCUIT, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector. | 12-03-2009 |
20100077262 | INFORMATION PROCESSING DEVICE AND ERROR PROCESSING METHOD - An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit. | 03-25-2010 |
20100191942 | Information processor and control method - A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction. | 07-29-2010 |
20100228507 | TRACE DEVICE AND TRACE METHOD FOR FAILURE ANALYSIS - A trace device for tracing data in an LSI includes a trace data storing unit that stores trace data, a trace target determination unit that determines whether to store trace data of one of a plurality of trace targets in the trace data storing unit based on an operating state of a system including the LSI and based on a failure occurrence report reported from any of the trace targets in response to an occurrence of an error in the trace target residing in the LSI and a trace target selection unit that selects the trace data to be stored in the trace data storing unit out of the trace data from the plurality of trace targets based on the determining by the trace target determination unit, and stores the selected trace data in the trace data storing unit. | 09-09-2010 |
20110047431 | Verification device, verification method, and verification program - A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet. | 02-24-2011 |
20110107157 | REGISTER ACCESS CONTROL METHOD AND CIRCUIT - A register access control circuit and method includes extracting data written to a plurality of registers by specifying the common address in response to read access to a common address, comparing the data extracted from the respective registers, and outputting the data extracted from one of the registers as read data when the data extracted from the respective registers match. | 05-05-2011 |
20110320683 | Information processing system, resynchronization method and storage medium storing firmware program - An information processing system includes sets of multiple processors performing processing synchronously. The system includes: a ROM storing a firmware program activating the processors to a synchronized state; a RAM defined by one address map; a firmware copying section copying the firmware program in the ROM to the RAM, on system boot; and a RAM address register storing an address of the RAM and of a copy destination of the firmware program. The system further includes: a RAM address storing section storing the address of the RAM and of the copy destination of the firmware program; a loss-of-synchronism detection section detecting loss of synchronism of the processors; and an address replacing section referring to the RAM address register upon detection of the loss of synchronism, thereby replacing an address for reading the stored firmware program, with the address of the RAM and of the copy destination of the firmware program. | 12-29-2011 |
20110320901 | DATA TRANSFER DEVICE AND CONTROL METHOD OF DATA TRANSFER DEVICE - A data transfer device includes a data transmitting circuit includes an error detection code generating unit generating an error detection code for detecting an error in the data, and a transmission unit transmitting the data and the error detection code together with retransmit enable information representing that corresponding data transmitted before the former data or transmitted next can be retransmitted, the data receiving circuit includes a reception unit receiving the transmitted data, the transmitted error detection code and the transmitted retransmit enable information, an error detection unit detecting the error in the received data based on the error detection code, an error data retaining unit retaining the data in which an error is detected when the reception unit receives the retransmit enable information, and an error data comparing unit that comparing the error detected data retained in the error data retaining unit with corresponding data that is retransmitted. | 12-29-2011 |
20130151173 | INTERPROCESSOR COMMUNICATION MEASUREMENT SYSTEM - An interprocessor communication measurement system for an information processing apparatus having a plurality of processors which may send data to the other processors through a plurality of communication channels, includes a socket which is connected with communication channels and electrically connects a processor attached thereto with the communication channels, a measurement node which is attached to the socket in place of the processor and electrically connected with the communication channels, wherein the measurement node includes a routing unit configured to send data destined for any one of the other processors to the one of the other processors through the communication channels and an intercepting unit configured to intercept data sent through the routing unit, and a storing unit configured to store data intercepted by the intercepting unit of the measurement node. | 06-13-2013 |
20130166671 | NODE CONTROLLER AND METHOD OF CONTROLLING NODE CONTROLLER - A node controller includes: a reception processor configured to receive a packet and to generate a read request or write data and a write request for requesting to write the write data, according to a destination and a type of the packet; a collected data processor configured to collect the received packet, to generate collected data according to the collected packet, and to generate a collected data write request for requesting to write the collected data; a switch configured to output the write data and the write request received from the reception processor or output the collected data and the collected data write request received from the collected data processor; and a memory controller configured to write the write data to a memory and to write the collected data to the memory in accordance with the collected data write request received from the switch. | 06-27-2013 |
20130297882 | CACHE MEMORY DEVICE, CONTROL UNIT OF CACHE MEMORY, INFORMATION PROCESSING APPARATUS, AND CACHE MEMORY CONTROL METHOD - A cache memory device including a cache memory that includes a plurality of entries and includes at least one block including data and a status representing a status of the data for each entry and a control unit that performs replacement of the data on each block of the cache memory, wherein the control unit includes a counter that counts the number of replacements by which the data is replaced in each entry for each entry and a switching unit that switches a replacement scheme of the data according to the number of replacements. | 11-07-2013 |
20140006720 | DIRECTORY CACHE CONTROL DEVICE, DIRECTORY CACHE CONTROL CIRCUIT, AND DIRECTORY CACHE CONTROL METHOD | 01-02-2014 |
20140095792 | CACHE CONTROL DEVICE AND PIPELINE CONTROL METHOD - A cache control device includes an entering unit, a first searching unit, a reading unit, a second searching unit, and a rewriting unit. The entering unit alternately enters, into a pipeline, a load request for reading a directory received from a processor and a store request for rewriting a directory received from the processor. When the first searching unit determines that the directory targeted by the load request is present in the first cache memory or the second cache memory, the reading unit reads the directory from the cache memory in which the directory is present. When the second searching unit determines that the directory targeted by the store request is present in the first cache memory, the rewriting unit rewrites the directory that is stored in the first cache memory. | 04-03-2014 |