Patent application number | Description | Published |
20090037916 | PROCESSOR - The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread. | 02-05-2009 |
20090051573 | VARIABLE-LENGTH-CODE DECODING DEVICE - A variable-length-code decoding device is operable to decode bit streams encoded in conformity with a plurality of coding systems. The device comprises a decoding unit ( | 02-26-2009 |
20090220009 | IMAGE DECODING DEVICE AND IMAGE DECODING METHOD - An image decoding device ( | 09-03-2009 |
20100100219 | FABRICATION SYSTEM OF SEMICONDUCTOR INTEGRATED CIRCUIT, FABRICATION DEVICE, FABRICATION METHOD, INTEGRATED CIRCUIT AND COMMUNICATION SYSTEM - A manufacturing system which can restrain the margin of a semiconductor integrated circuit. | 04-22-2010 |
20100128801 | IMAGE DECODING DEVICE, IMAGE DECODING SYSTEM, IMAGE DECODING METHOD, AND INTEGRATED CIRCUIT - A segment allocation determination unit | 05-27-2010 |
20100239024 | IMAGE DECODING DEVICE AND IMAGE DECODING METHOD - To decode coded pictures each of which has dependencies within the picture, using conventional decoding circuits and without deteriorating the efficiency in parallel processing. | 09-23-2010 |
20100266049 | IMAGE DECODING DEVICE - An image decoding apparatus pertaining to the present invention includes a plurality of decoders. The image decoding apparatus (i) divides image data to decode into a plurality of pieces of partial data, (ii) acquires attribute information pieces each affecting decoding processing time of a corresponding one of the plurality of pieces of partial data, (iii) determines which of the plurality of decoders is caused to decode which of the plurality of pieces of partial data based on the attribute information pieces on the plurality of pieces of partial data and (iv) causes two or more of the plurality of decoders to decode two or more corresponding pieces of the partial data in parallel. | 10-21-2010 |
20110131442 | TRACING APPARATUS AND TRACING SYSTEM - A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of the processing units: a counting unit configured to obtain and output a counter value for the corresponding processing unit, the counter value obtained by counting clock signals that are input to the processing unit at an operating frequency thereof; a counter value conversion unit configured to obtain and output a converted counter value for the corresponding processing unit, the converted counter value obtained by converting the counter value based on the assumption that the processing unit has a given reference operating frequency; and an adding unit configured to acquire an operational information set from the corresponding processing unit, and to add the converted counter value to the operational information set. | 06-02-2011 |
20110135285 | IMAGE CODING APPARATUS, METHOD, INTEGRATED CIRCUIT, AND PROGRAM - An image coding apparatus ( | 06-09-2011 |
20110138092 | ARBITRATION DEVICE, ARBITRATION SYSTEM, ARBITRATION METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND IMAGE PROCESSING DEVICE - Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request. | 06-09-2011 |
20110235716 | DECODING APPARATUS, DECODING METHOD, PROGRAM AND INTEGRATED CIRCUIT - A decoding apparatus ( | 09-29-2011 |
20120063693 | IMAGE DECODING DEVICE, IMAGE ENCODING DEVICE, IMAGE DECODING CIRCUIT, AND IMAGE DECODING METHOD - A decoding apparatus ( | 03-15-2012 |
20120147959 | MOVING IMAGE DECODING APPARATUS, MOVING IMAGE CODING APPARATUS, MOVING IMAGE DECODING CIRCUIT, AND MOVING IMAGE DECODING METHOD - A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit ( | 06-14-2012 |