Patent application number | Description | Published |
20080259694 | Semiconductor Device - A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) | 10-23-2008 |
20080265300 | Semiconductor device having plural dram memory cells and a logic circuit and method for manufacturing the same - A memory cell capacitor (C | 10-30-2008 |
20090027984 | SEMICONDUCTOR DEVICE - The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL. | 01-29-2009 |
20090116363 | INFORMATION STORAGE DEVICE AND STORAGE MEDIA - In an information memory apparatus having minute areas for storing information arranged in x, y and z directions three-dimensionally, parallel rays are irradiated to a memory area MA in a direction perpendicular to a z-axis to take projection images of the memory area MA while rotating the memory area MA around the z-axis little by little. The light rays irradiated at this time have a size which covers at least a direction of an x-y plane of the memory area. A computation unit PU finds data and addresses of minute areas distributed three-dimensionally by performing computation based upon the principle of computer tomography on the projection images. As for data writing, a change is given to optical transmissivity or light emission characteristics by irradiating laser light focused by a lens OL placed outside the memory area to a desired minute area and causing heat denaturation within the pertinent minute area. | 05-07-2009 |
20090129173 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting. | 05-21-2009 |
20090154304 | Information memory device and memory medium - An information memory device using an electromagnetic-wave resonance phenomenon is provided to achieve both high density and long-period storage of stored data. Memory cells are three-dimensionally arranged in the inside of a solid-like medium which is not contacted with a surface of the medium, and the memory cell has resonance characteristics to electromagnetic waves depending on the space coordinates of the memory cell. For the medium, a material is selected so that an electromagnetic wave having the resonance frequency of the memory cell. By observing absorption spectra of the irradiated electromagnetic wave or emission spectra after the absorption, three-dimensional space coordinates of the memory cell are calculated. | 06-18-2009 |
20100084698 | SEMICONDUCTOR DEVICE HAVING PLURAL DRAM MEMORY CELLS AND A LOGIC CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - A memory cell capacitor (C | 04-08-2010 |
20100309741 | SEMICONDUCTOR DEVICE - The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL. | 12-09-2010 |
20100314676 | SEMICONDUCTOR DEVICE HAVING PLURAL DRAM MEMORY CELLS AND A LOGIC CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - A memory cell capacitor (C | 12-16-2010 |
20110158062 | INFORMATION PROCESSING SYSTEM - In an information storage device in which small compartments each for storing information are arranged three-dimensionally inside a solid body, the solid body having at least one pair of parallel planar portions on its surface is used for a memory medium. The information to be stored is divided into bits and stored in discrete minute areas that distribute three-dimensionally inside the memory medium. Anisotropy is given to the pitch of the memory cell and the pitch in a direction right-angled to the planar portion is made larger than the pitch in the parallel direction. Moreover, the data such that given n-bits are used as a unit is converted into a digital format such that m-bits larger than n are used as a unit and the number of included ā1sā is smaller than n, which is recorded in the memory medium. When recording the data on the medium, pieces of the data expressed by the m-bits are arranged on the plate in the right-angle direction. | 06-30-2011 |
20110211436 | Information Processor Device and Storage Medium - In an information storage device in which small partitions for storing information are three-dimensionally placed inside a solid, the invention aims at long-period storage, robustness, and rapid information reading. Accordingly, the stored three-dimensional information is divided into two-dimensional data for each layer, and two-dimensional inverse Fourier transform is previously applied for the two-dimensional data. The two-dimensional data is recorded in each layer in a Z direction inside a storage medium which is solid. When the information is reproduced, electromagnetic waves are irradiated to a storage area MA as gradually rotating the storage area MA around a z axis, and projection images of all layers during the rotation are obtained from response. By applying one-dimensional Fourier transform for a plurality of projection images obtained as described above, the recorded original three-dimensional information is rapidly reproduced. | 09-01-2011 |
20120087178 | SEMICONDUCTOR MEMORY DEVICE - Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element. | 04-12-2012 |
20120294081 | SEMICONDUCTOR DEVICE - In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL. | 11-22-2012 |
20130194902 | INFORMATION PROCESSING SYSTEM - An information storage device has small compartments for storing information in a solid body and can be used as a memory medium. The solid body can have at least one pair of parallel planar portions on its surface. The information is divided into bits and stored in discrete minute areas that are distributed three-dimensionally inside the memory medium. The data can be converted into a digital format for storage to regulate the number of ā1sā recorded in a direction of the memory medium. | 08-01-2013 |