Patent application number | Description | Published |
20080285354 | Self reference sensing system and method - A self sensing reference system and method are described. The self sensing reference systems and methods facilitate efficient accurate access to information. In one embodiment, a self sensing reference system includes a main cascode component, a self referencing component, and a comparison verification component. The main cascode component receives input on a first current value and a second current value. The self referencing component establishes a plurality of data indications wherein a first data indication is established based upon a comparison of the first current value to the second current value. A comparison verification component verifies a second data indication. | 11-20-2008 |
20090180330 | NON-VOLATILE MEMORY DEVICE AND METHODS OF USING - The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed. | 07-16-2009 |
20090201724 | MEMORY DEVICE AND METHOD THEREOF - A device and corresponding method of using a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier is disclosed. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent disclosing time can be achieved at a sense node of a sense amplifier. | 08-13-2009 |
20100238731 | PARTIAL LOCAL SELF-BOOSTING OF A MEMORY CELL CHANNEL - A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage. | 09-23-2010 |
20110286276 | PARTIAL LOCAL SELF BOOSTING FOR NAND - A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line. | 11-24-2011 |
20120057406 | FLASH MEMORY APPARATUS - A flash memory apparatus includes a plurality of memory sectors and a plurality of path transistors, and each memory sector has a local low voltage line, and each path transistor corresponds to one of the memory sectors, and the path transistors are installed in an alignment direction of the memory sectors. One of the path transistors is installed between two adjacent memory sectors, whose gate is connected to a sector select signal line, and whose drain is connected to the local low voltage line of the corresponding memory sector, and whose source is connected to a global low voltage line, and the global low voltage line is installed at an angle substantially equal to 90 degrees across the gate, so as to save the area occupied by peripheral circuits in the path transistors, and lower the manufacturing cost of the flash memory apparatus. | 03-08-2012 |
20120170377 | LOCAL WORD LINE DRIVER AND FLASH MEMORY ARRAY DEVICE THEREOF - In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units. | 07-05-2012 |
20140056088 | METHOD OF IDENTIFYING DAMAGED BITLINE ADDRESS IN NON-VOLATILE MEMORY DEVICE - A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line. | 02-27-2014 |
20140078832 | NON-VOLATILE MEMORY HAVING DISCRETE ISOLATION STRUCTURE AND SONOS MEMORY CELL, METHOD OF OPERATING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory. | 03-20-2014 |
20140104957 | PARTIAL LOCAL SELF BOOSTING FOR NAND - A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line. | 04-17-2014 |