Patent application number | Description | Published |
20100164055 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER - A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion. | 07-01-2010 |
20100167495 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER - A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion. | 07-01-2010 |
20130327384 | MULTI-JUNCTION SOLAR CELL AND MANUFACTURING METHOD THEREFOR - The present invention provides a multi-junction solar cell capable of increasing the degree of freedom of the selection of compound semiconductors. The multi-junction solar cell | 12-12-2013 |
Patent application number | Description | Published |
20090051012 | Through-hole interconnection structure for semiconductor wafer - A through-hole interconnection structure for a semiconductor wafer, in which: the each wafer includes at least a first wafer and a second wafer electrically connected to the first wafer; an electrical signal connecting section of the second wafer is provided to protrude from a bonding surface of the second wafer, the bonding surface being bonded with the first wafer; and the electrical signal connecting section has a cross section with a curved line or two or more straight lines extending in different directions when the second wafer is seen along a cross section parallel to the bonding surface. | 02-26-2009 |
20090057890 | SEMICONDUCTOR DEVICE - In this semiconductor device, connection parts between wafers are electrically insulated from each other, and a junction face shape of second electrical signal connection parts is larger than the shape of a positioning margin face that is formed by an outer shape when the periphery of a minimum junction face, which has half the area of a junction area of the first electrical signal connection part, is enclosed by a same width dimension as a positioning margin dimension between the first wafer and the second wafer. | 03-05-2009 |
20090061659 | THROUGH-HOLE INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR WAFER - A through-hole interconnection structure for a semiconductor wafer in which plural wafers are bonded together each having a substrate with devices provided thereon, an electrical signal connecting section is provided on a bonding surface of each wafer, the bonding surface being for bonding with other wafers, and the electrical signal connecting section is electrically connected to an electrical signal connecting section provided on another of the oppositely-facing wafers to form a desired semiconductor circuit, the through-hole interconnection structure being provided with: a through-hole interconnection section which has a through-hole protruding section which protrudes from the bonding surface to conduct the opposite surfaces of the wafer, the through-hole interconnection section being one of the oppositely-facing electrical signal connecting sections; and a bump which is the other of the oppositely-facing electrical signal connecting sections, wherein: the through-hole protruding section has an oppositely-placed pair of wiring side walls which extend from the bonding surface toward the another wafer; an end of the through-hole interconnection section is extended to reach an inside of the bump; and the bump is placed between the pair of wiring side walls. | 03-05-2009 |