Patent application number | Description | Published |
20090302293 | SEMICONDUCTOR DEVICE - On the same semiconductor substrate | 12-10-2009 |
20100012917 | SEMICONDUCTOR DEVIC - On an insulating film ( | 01-21-2010 |
20100015755 | MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - In a step of forming an InGeSbTe film which contains GeSbTe made of germanium (Ge), antimony (Sb) and tellurium (Te) as its base material and to which indium (In) is added, an InGeSbTe film is formed by sputtering on a semiconductor substrate while keeping a temperature of the semiconductor substrate between an in-situ crystallization temperature of GeSbTe serving as the base material and an in-situ crystallization temperature of InGeSbTe. As a result, it is possible to suppress the failure that the phase separation occurs in the InGeSbTe film during the following manufacturing process. | 01-21-2010 |
20100072451 | SEMICONDUCTOR DEVICE - A recording layer | 03-25-2010 |
20100096613 | SEMICONDUCTOR DEVICE - A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony. | 04-22-2010 |
20100171087 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME - In a semiconductor device including a phase change memory element whose memory layer is formed of a phase change material of M (additive element)-Ge (germanium)-Sb (antimony)-Te (tellurium), both of high heat resistance and stable data retention property are achieved. The memory layer has a fine structure with a different composition ratio therein, and an average composition of M | 07-08-2010 |
20100182828 | SEMICONDUCTOR STORAGE DEVICE - There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory. | 07-22-2010 |
20110049454 | SEMICONDUCTOR DEVICE - In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc. | 03-03-2011 |
20120211718 | SEMICONDUCTOR STORAGE DEVICE - There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory. | 08-23-2012 |