Patent application number | Description | Published |
20080212683 | Image Decoding Device, Image Encoding Device and System LSI - An image decoding device according to the present invention is an image decoding device responding to decoding of an image encoding method selecting an encoding table and an encoding format to use according to the kind of a parameter included in encoded data and comprises a bit stream processing unit converting a bit stream of the encoded data into an intermediate format and an image processing unit decoding data converted into the intermediate format and converting the same into image data. The bit stream processing unit and the image processing unit start independently. An image encoding device according to the present invention, in the same manner, comprises an image processing unit converting image data to be encoded into an intermediate format and a bit stream processing unit encoding the data converted into the intermediate format and converting the same into a bit stream. Thereby, image encoding and decoding processings with a low operation frequency and low power consumption is realized. | 09-04-2008 |
20080294878 | PROCESSOR SYSTEM AND EXCEPTION PROCESSING METHOD - When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit and rewrites a value of a program counter to a value of an error address register. By this means, the branching process by an error interrupt is realized. In this case, when the error is detected, the process of saving the value of the program counter at the time of error occurrence is not performed, and a specific save register and a control circuit for the recovery to the address at the time of the error occurrence after the end of the error processing are not provided. | 11-27-2008 |
20090237278 | VARIABLE LENGTH CODE DECODING DEVICE AND DECODING METHOD - A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that is given a start address and an initial reference bit length of the table memory; and sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table. | 09-24-2009 |
20110080308 | VARIABLE LENGTH CODE DECODING DEVICE AND DECODING METHOD - A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table. | 04-07-2011 |
20120326899 | VARIABLE LENGTH CODE DECODING DEVICE AND DECODING METHOD - Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses. | 12-27-2012 |
Patent application number | Description | Published |
20090144527 | STREAM PROCESSING APPARATUS, METHOD FOR STREAM PROCESSING AND DATA PROCESSING SYSTEM - The present invention provides a stream processing apparatus capable of improving the processing performance in the case of continuously processing a plurality of data streams. A control stream, different from a data stream, is prepared, and a program and a parameter are updated in advance in accordance with the control stream. Double buffer areas are prepared in a memory of the stream processing apparatus into which the program and the parameter are stored. The location of the data stream to be input is written in the control stream, and buffers for reading the data stream are multiplexed so as to read in advance the top portion of the data stream to be processed next. | 06-04-2009 |
20090304078 | VARIABLE LENGTH DECODER AND ANIMATION DECODER THEREWITH - The variable length decoder has a memory device including a plurality of lookup tables, and sequentially decodes codewords of variable-length codes using the memory device. The decoded values corresponding to the codewords and control information pieces are stored in the lookup tables. In decoding one codeword, one lookup table is selected from among the plurality of lookup tables. In the decode, one decoded value corresponding to the one codeword, and a control information piece for selecting a next lookup table depending on the decoded value and used for a next decode are produced from the selected lookup table in response to the one codeword in parallel. | 12-10-2009 |
20100080288 | VIDEO COMPRESSION CODING METHOD AND APPARATUS - A first delay memory is input with an input image frame output from a ME (motion estimation) processor, and delays output to a first adder for carrying out a prediction residual generation process a predetermined time period. A second delay memory is input with an inter-prediction luminance image frame, and delays output to a prediction selection circuit a predetermined time period. A third delay memory is input with motion vector information output from the ME processor, and delays output of the motion vector information to an inter-prediction chrominance image creation processor a predetermined time period. | 04-01-2010 |
20100135381 | ENCODING/DECODING DEVICE AND VIDEO TRANSMISSION SYSTEM - The present invention relates to a video transmission system that uses an encoding/decoding technique. An object of the present invention is to refrain from using a memory for storing decoded image data, avoid a decoder input buffer problem (buffer overflow or underflow) with ease, achieve cost reduction, and provide enhanced image quality. In the video transmission system with an encoding/decoding device, a reference signal for adjusting a synchronization schedule of the entire system is generated and supplied to various sections. In addition, a timing adjustment amount for adjusting the synchronization schedule for the reference signal is generated by a decoder and supplied to a camera. | 06-03-2010 |
20110013696 | MOVING IMAGE PROCESSOR AND PROCESSING METHOD FOR MOVING IMAGE - A moving image processor includes a first and a second moving image processing unit which are able to perform parallel operation, and a data transfer unit having a first buffer and a second buffer. The first moving image processing unit processes macroblocks MB | 01-20-2011 |
20110238964 | DATA PROCESSOR - The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register. | 09-29-2011 |