Patent application number | Description | Published |
20130052815 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function. | 02-28-2013 |
20130062767 | VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME - An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall. | 03-14-2013 |
20130080980 | METHOD FOR CHECKING AND FIXING DOUBLE-PATTERNING LAYOUT - A method including receiving layout data representing the plurality of patterns, the layout data including a plurality of layers and identifying spaces between adjacent patterns in at least one layer of the plurality of layers which violate a G | 03-28-2013 |
20130084680 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD, SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD). | 04-04-2013 |
20130093504 | REFERENCE VOLTAGE GENERATORS, INTEGRATED CIRCUITS, AND METHODS FOR OPERATING THE REFERENCE VOLTAGE GENERATORS - A reference voltage generator is described. The reference voltage generator includes a proportional to absolute temperature (PTAT) current source, the PTAT current source being capable of providing a first current that is proportional to a temperature. The reference voltage generator further includes a current mirror comprising a first transistor and a second transistor, the current mirror configured to generate a second current proportional to the first current, wherein a ratio of the first current to the second current is equal to a ratio of a gate width of the first transistor to a gate width of the second transistor. The reference voltage generator further includes a voltage divider, the voltage divider being capable of receiving the second current, the voltage divider capable of outputting a reference voltage, the reference voltage being substantially independent from a change of the temperature. | 04-18-2013 |
20130095647 | BACKSIDE BEVEL PROTECTION - A method of fabricating an integrated circuit device is provided. The method includes forming a replacement gate structure with a dummy polysilicon layer on a first surface of a substrate. The method further includes depositing a dielectric layer by a thermal process to form offset spacers on two opposing sides of the replacement gate structure, wherein the dielectric layer is deposited on the first surface and a second surface opposing the first surface of the substrate. The method further includes removing the dummy polysilicon layer from the replacement gate structure, wherein the dielectric layer on the second surface of the substrate protects the second surface of the substrate during the removing step. | 04-18-2013 |
20130134482 | SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE - A method of making a high-electron mobility transistor (HEMT) includes forming an unintentionally doped gallium nitride (UID GaN) layer over a silicon substrate, a donor-supply layer over the UID GaN layer, a gate, a passivation layer over the gate and portions of the donor-supply layer, an ohmic source structure and an ohmic drain structure over the donor-supply layer and portions of the passivation layer. The source structure includes a source contact portion and an overhead portion. The overhead portion overlaps the passivation layer between the source contact portion and the gate, and may overlap a portion of the gate and a portion of the passivation layer between the gate and the drain structure. | 05-30-2013 |
20130161689 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well. | 06-27-2013 |