Patent application number | Description | Published |
20130019954 | SLURRY SYSTEM FOR SEMICONDUCTOR FABRICATION - A slurry feed system suitable for chemical mechanical planarization (CMP) processes in a semiconductor fabrication facility and related method. The slurry feed system includes a valve manifold box having a discharge piping header fluidly connected to at least one CMP station and a first slurry supply train. The first slurry supply train may include a slurry mixing tank, day tank, and at least two slurry feed pumps arranged in series pumping relationship. The first slurry supply train defines a first slurry piping loop. In one embodiment, a second slurry supply train defining a second slurry piping loop is provided. The valve manifold box is operable to supply slurry from either or both of the first and second slurry piping loops to the CMP station. | 01-24-2013 |
20130023083 | METHOD FOR FORMING STRUCTURE FOR REDUCING NOISE IN CMOS IMAGE SENSORS - A method and device is disclosed for reducing noise in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion includes an opaque layer or a black light filter layer in conjunction with an opaque layer, covering the support feature section. The light blocking portion may also cover a peripheral portion of the light sensing structure. The method for forming the CMOS image sensors includes using film patterning and etching processes to selectively form the opaque layer and the black light filter layer where the light blocking portion is desired, but not over the active section. The method also provides for forming microlenses over the photosensors in the active section. | 01-24-2013 |
20130032450 | HIGH EFFICIENCY BUFFER STOCKER - A high-efficiency buffer stocker is disclosed. The buffer stocker includes an overhead transport track for supporting overhead transport vehicles carrying wafer containers and at least one conveyor system or conveyor belt provided beneath the overhead transport track for receiving the wafer containers from the overhead transport vehicles on the overhead transport track. The buffer stocker is capable of absorbing the excessive flow of wafer containers between a processing tool and a stocker, for example, to facilitate the orderly and efficient flow of wafers between sequential process tools in a semiconductor fabrication facility, for example. | 02-07-2013 |
20130044018 | METHOD AND CIRCUIT FOR CONTINUOUS-TIME DELTA-SIGMA DAC WITH REDUCED NOISE - A continuous-time delta-sigma digital-to-analog converter (DAC) includes a first delta-sigma modulator configured to quantize a most significant bit or bits of a digital input signal and produce a first quantization error signal, and a second multi-stage delta-sigma modulator configured to quantize less significant bits of the digital input signal. A first DAC is coupled to an output of the first delta-sigma modulator, and a second DAC is coupled to an output of the second noise-shaping filter. The second DAC has a greater resolution than the first DAC. A low pass output filter is coupled to a sum of an output of the first DAC and an output of the second DAC. | 02-21-2013 |
20130064017 | CONCURRENT OPERATION OF PLURAL FLASH MEMORIES - A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. | 03-14-2013 |
20130074019 | METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT TWO LEVELS - A method for verifying functionality of a system-on-chip (SoC) comprises modeling a system block in first and second models at a first level and a second level lower than the first level, respectively. A stimulus transaction is generated at a first testbench at the first level. The stimulus transaction is transmitted from the first testbench to a second testbench at the second level. The stimulus transaction is transformed into a first response transaction, using the first model, at the first level. The stimulus transaction received at the second testbench is transformed into a second response transaction, using the second model, at the second level. Functionality of the SoC at the first and second levels is verified based on the first and second response transactions. | 03-21-2013 |
20130113958 | COLOR IMAGE SENSOR ARRAY WITH COLOR CROSSTALK TEST PATTERNS - An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration. | 05-09-2013 |
20130126982 | EPITAXIAL PROCESS FOR FORMING SEMICONDUCTOR DEVICES - A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate. | 05-23-2013 |
20130130461 | EPITAXIAL PROCESS FOR FORMING SEMICONDUCTOR DEVICES - A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate. | 05-23-2013 |
20130136149 | TEMPERATURE SENSOR WITH DIGITAL TRIM AND TRIMMING METHOD THEREOF - A method for calibrating a temperature sensor comprises: receiving first and second reference voltages from respective first and second tap points within a string of sequentially connected resistive devices of the temperature sensor. Each resistive device has a resistance that varies as a function of temperature. The receiving is performed at two or more known temperatures. A respective code is output corresponding to each respective one of the two or more known temperatures, based on the first and second reference voltages. At least one of the tap points is adjusted, based on the two or more known temperatures and the respective output codes. | 05-30-2013 |
20130141145 | CLOCK AND DATA RECOVERY CIRCUIT - The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal. | 06-06-2013 |
20130155751 | MEMORY DEVICES HAVING BREAK CELLS - A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage. | 06-20-2013 |
20130155785 | MEMORY MACRO CONFIGURATION AND METHOD - A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value. A plurality of output drivers are coupled to the segment decoder circuit and to respective ones of the outputs. The plurality of output drivers are configured to selectively output data from the respective outputs of each of the respective activated memory array segments. | 06-20-2013 |
20130167095 | STACKED DIE INTERCONNECT VALIDATION - A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns. | 06-27-2013 |
20130169326 | GATED VOLTAGE-CONTROLLED OSCILLATOR AND CLOCK AND DATA RECOVERY CIRCUIT - A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal. | 07-04-2013 |