Patent application number | Description | Published |
20090108886 | Semiconductor Device - A semiconductor device includes a circuit having a first data holding node and a second data holding node; a first MOS field-effect transistor coupled to the first data holding node; a second MOS field-effect transistor coupled to the second data holding node; and a clock generation circuit coupled to a first gate electrode of the first MOS field-effect transistor for outputting a clock signal, wherein the first gate electrode is coupled to the second data holding node via the second MOS field-effect transistor, and a second gate electrode of the second MOS field-effect transistor is coupled to the first data holding node via the first MOS field-effect transistor. | 04-30-2009 |
20090121764 | SEMICONDUCTOR DEVICE - A semiconductor device has a first latch circuit, a second latch circuit configured to receive an output of the first latch circuit, a first switching element provided between the first latch circuit and the second latch circuit, a feedback line for feeding data held by the second latch circuit to the first latch circuit, and a second switching element provided on the feedback line. | 05-14-2009 |
20090128196 | Data Holding Circuit - A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element. | 05-21-2009 |
20090140764 | Latch Circuit - A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals. | 06-04-2009 |
20090243686 | LATCH CIRCUIT AND ELECTRONIC DEVICE - A latch circuit includes: four or more gates; three input terminals and one or two output terminals which are connected to at least one of the four or more gates; a feedback circuit in which respective input terminals of the four or more gates are connected to output terminals of at least another two of the four gates; and a data inverting gate which, when all data input into the three input terminals is the same, outputs inverted data of the data from the output terminals, and when all the data input into the three input terminals is not the same, retains previous data. | 10-01-2009 |
20100213998 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device having: a latch circuit ( | 08-26-2010 |
20100308881 | SEMICONDUCTOR DEVICE - A semiconductor device has a first latch circuit, a second latch circuit configured to receive an output of the first latch circuit, a first switching element provided between the first latch circuit and the second latch circuit, a feedback line for feeding data held by the second latch circuit to the first latch circuit, and a second switching element provided on the feedback line. | 12-09-2010 |
20110006803 | LATCH CIRCUIT - A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals. | 01-13-2011 |
20120038386 | LATCH CIRCUIT - A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals. | 02-16-2012 |