Patent application number | Description | Published |
20090045451 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make the second conductive film into a second conductor; forming an interlayer insulating film (a third insulating film) covering the second conductor; forming a first hole in the interlayer insulating film on the contact region; and forming a conductive plug, which is electrically connected with the contact region, in the first hole. | 02-19-2009 |
20090102010 | SEMICONDUCTOR DEVICE WITH STI AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area. | 04-23-2009 |
20090121318 | Semiconductor device, DRAM integrated circuit device, and method of producing the same - A semiconductor device with a multi-layer wiring structure includes a first conductive region: a second conductive region that has an upper surface located in a higher position than the first conductive region with respect to the substrate; an insulating that covers the first and second conductive regions; a wiring groove that is formed in the insulating film so as to expose the second conductive region; a contact hole that is formed in the insulating film so as to expose the first conductive region; and a wiring pattern that fills the wiring groove and the contact hole. In this semiconductor device, the upper surface of the wiring pattern is located on the same plane as the upper surface of the insulating film. | 05-14-2009 |
20090154216 | Semiconductor memory device and semiconductor device group - A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region. | 06-18-2009 |
20100105180 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING IMPROVED PUNCH-THROUGH RESISTANCE AND PRODUCTION METHOD THEREOF, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A LOW-VOLTAGE TRANSISTOR AND HIGH-VOLTAGE TRANSISTOR - An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well. | 04-29-2010 |
20100238716 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE GROUP - A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region. | 09-23-2010 |
20100283092 | SEMICONDUCTOR DEVICE - The semiconductor device includes a first conductor formed over a semiconductor substrate; a first insulator formed over the first conductor; a second insulator formed over the first insulator, the second insulator having an etching characteristic different from an etching characteristic of the first insulator; a second conductor formed on the second insulator, the second conductor being in contact with the second insulator; a third insulator formed over the second conductor, the third insulator having an etching characteristic different from the etching characteristic of the second insulator; a first contact hole formed through the third insulator and the second conductor, the first contact hole reaching the second insulator; a third conductor formed in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; a second contact hole formed through the third insulator and the first insulator, the second contact hole reaching the first conductor; and a fourth conductor formed in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor. | 11-11-2010 |
20100285653 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device includes a first conductor over a semiconductor substrate; forming a first insulator over the first conductor; forming a second insulator, having an etching characteristic different from an etching characteristic of the first insulator, over the first insulator; forming a second conductor on the second insulator, the second conductor being in contact with the second insulator; forming a third insulator, having an etching characteristic different from the etching characteristic of the second insulator, over the second conductor; forming a first contact hole though the third insulator and the second conductor, the first contact hole exposing the second insulator; forming a second contact hole through the third insulator and the first insulator, the second contact hole exposing the first conductor; forming a third conductor in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; forming a fourth conductor in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor. | 11-11-2010 |
20100308420 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film. | 12-09-2010 |
20100320543 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers. | 12-23-2010 |
20110037116 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode. | 02-17-2011 |
20110073950 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a first MIS transistor including a gate insulating film | 03-31-2011 |
20110108925 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a first MIS transistor including a gate insulating film | 05-12-2011 |
20110111567 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a first MIS transistor including a gate insulating film | 05-12-2011 |
20110198707 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500 ° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers. | 08-18-2011 |
20110244650 | SEMICONDUCTOR DEVICE WITH STI AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area. | 10-06-2011 |