Patent application number | Description | Published |
20090026612 | SEMICONDUCTOR PACKAGE HAVING AN IMPROVED CONNECTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package having an improved connection structure and a method for manufacturing the same is described. The semiconductor package includes a substrate having a substrate body, connection pads that are located on one surface of the substrate body, and ball lands that are located on the other surface of the substrate body opposite the one surface. The ball lands are electrically connected to the connection pads. A semiconductor chip having bumps that are formed to correspond to the connection pads is connected to the substrate. An anisotropic conductive member having an insulation element is interposed between the substrate and the semiconductor chip to connect the substrate and the semiconductor chip. Electrically flowable conductive particles within the insulation element flow in the insulation element according to applied electric fields so as to arrange the electrically flowable conductive particles between the connection pads and the bumps. | 01-29-2009 |
20090166836 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 07-02-2009 |
20090321953 | CIRCUIT SUBSTRATE HAVING CIRCUIT WIRE FORMED OF CONDUCTIVE POLARIZATION PARTICLES, METHOD OF MANUFACTURING THE CIRCUIT SUBSTRATE AND SEMICONDUCTOR PACKAGE HAVING THE CIRCUIT WIRE - A circuit substrate includes a substrate body having a first terminal and a second terminal separated from the first terminal. A circuit wire includes a wiring unit for electrically connecting the first and second terminals by electrically connecting conductive polarization particles that include a first polarity and a second polarity that is opposite to the first polarity. The circuit wire also includes an insulation unit for insulating the wiring unit. | 12-31-2009 |
20100065958 | PAD REDISTRIBUTION CHIP FOR COMPACTNESS, METHOD OF MANUFACTURING THE SAME, AND STACKED PACKAGE USING THE SAME - A substrate includes a substrate; a number of pad redistribution chips stacked on the substrate and on one another after being rotated 90° in a predetermined direction relative to one another, the pad redistribution chips having a number of center pads positioned at the center thereof, a number of (+) edge pads positioned on an end thereof while corresponding to those of the center pads lying in (+) direction from a middle center pad located in the middle of the center pads, a number of (−) edge pads positioned on the other end thereof while corresponding to those of the center pads lying in (−) direction with symmetry to those of the center pads lying in the (+) direction, and a number of traces for electrically connecting the center pads to the corresponding (±) edge pads, respectively; a flexible PCB for electrically connecting the substrate to the pad redistribution chips; and an anisotropic dielectric film for electrically connecting the pad redistribution chips to the flexible PCB and the substrate to the flexible PCB. | 03-18-2010 |
20100140757 | SEMICONDUCTOR PACKAGE HAVING AN ANTENNA WITH REDUCED AREA AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes an electromagnetic shielding member for shielding electromagnetic waves. An antenna is disposed on an upper face of the electromagnetic shielding member and includes an antenna part with a plurality of conductive particles electrically connected with each other and an insulation part disposed on the upper face of the electromagnetic shielding member and insulating the antenna part. Ball lands are disposed on the electromagnetic shielding member and are electrically connected with the antenna part. A Radio Frequency Identification (RFID) chip is electrically connected to the ball lands. | 06-10-2010 |
20110121454 | STACK SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members. | 05-26-2011 |
20110233795 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 09-29-2011 |
20110254167 | STACK PACKAGE HAVING FLEXIBLE CONDUCTORS - A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package. | 10-20-2011 |
20110275181 | SEMICONDUCTOR PACKAGE HAVING AN ANTENNA WITH REDUCED AREA AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes an electromagnetic shielding member for shielding electromagnetic waves. An antenna is disposed on an upper face of the electromagnetic shielding member and includes an antenna part with a plurality of conductive particles electrically connected with each other and an insulation part disposed on the upper face of the electromagnetic shielding member and insulating the antenna part. Ball lands are disposed on the electromagnetic shielding member and are electrically connected with the antenna part. A Radio Frequency Identification (RFID) chip is electrically connected to the ball lands. | 11-10-2011 |
20120061834 | SEMICONDUCTOR CHIP, STACKED CHIP SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND FABRICATING METHOD THEREOF - A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole. | 03-15-2012 |
20120088336 | SEMICONDUCTOR PACKAGE HAVING AN IMPROVED CONNECTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package having an improved connection structure and a method for manufacturing the same is described. The semiconductor package includes a substrate having a substrate body, connection pads that are located on one surface of the substrate body, and ball lands that are located on the other surface of the substrate body opposite the one surface. The ball lands are electrically connected to the connection pads. A semiconductor chip having bumps that are formed to correspond to the connection pads is connected to the substrate. An anisotropic conductive member having an insulation element is interposed between the substrate and the semiconductor chip to connect the substrate and the semiconductor chip. Electrically flowable conductive particles within the insulation element flow in the insulation element according to applied electric fields so as to arrange the electrically flowable conductive particles between the connection pads and the bumps. | 04-12-2012 |
20120139128 | SEMICONDUCTOR PACKAGE AND A METHOD FOR SELECTING A CHIP IN THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip formed with a first through-silicon via; a second semiconductor chip stacked over the first semiconductor chip and formed with a second through-silicon via; and a cantilever formed over the first semiconductor chip and electrically connected to the first through-silicon via or the second through-silicon via according to an electrical signal. | 06-07-2012 |
20120154020 | STACK PACKAGE AND METHOD FOR SELECTING CHIP IN STACK PACKAGE - A stack package having stacked chips includes first voltage dropping units respectively formed in the chips; second voltage dropping units respectively formed in the chips; first signal generation units connected in parallel to a first line formed by connecting the first voltage dropping units in series, respectively formed in the chips, and configured to apply high level signals according to a voltage of the first line; second signal generation units connected in parallel to a second line formed by connecting in series the second voltage dropping units, respectively formed in the chips, and configured to apply high level signals according to a voltage of the second line; and chip selection signal generation units respectively formed in the chips, and configured to combine signals outputted from the first signal generation units and the second signal generation units and generate chip selection signals. | 06-21-2012 |
20120299169 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 11-29-2012 |
20120299199 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 11-29-2012 |
20130001779 | STACK PACKAGE HAVING FLEXIBLE CONDUCTORS - A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package. | 01-03-2013 |
20130292820 | ELECTRONIC DEVICE PACKAGES INCLUDING BUMP BUFFER SPRING PADS AND METHODS OF MANUFACTURING THE SAME - Electronic device packages and related methods are provided. The electronic device package includes a first substrate having a first contact portion disposed thereon, a bump having a first contact surface connected to the first contact portion and a second contact surface disposed opposite to the first contact surface, and a buffer spring pad portion between the first contact portion of the first substrate and the first contact surface of the bump. The buffer spring pad portion includes at least two different conductive material layers which are stacked. | 11-07-2013 |