Patent application number | Description | Published |
20120133048 | SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector. | 05-31-2012 |
20120156823 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth. | 06-21-2012 |
20120326307 | STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device including a plurality of semiconductor chips stacked vertically, a plurality of scribe lane elements each forming a step with a semiconductor chip of the plurality of semiconductor chips and respectively formed on a side surface of each of the plurality of semiconductor chips, a redistribution element respectively formed on each of the plurality of semiconductor chips and the scribe lane elements, and a signal connection member formed on the side surface of each of the plurality of semiconductor chips and electrically connecting the redistribution elements. | 12-27-2012 |
20130001797 | PACKAGE ON PACKAGE USING THROUGH SUBSTRATE VIAS - A package on package (PoP) employing a through substrate via (TSV) technique in order to reduce the size of a semiconductor chip, has vertically narrow pitches, and forms a higher number of connection terminals. The PoP include a first substrate with a recess disposed in a first surface of the substrate, and a semiconductor chip disposed at the recess. The PoP also includes a semiconductor package connected to the first semiconductor package. The first substrate includes TSVs for electronically connecting the semiconductor package and the semiconductor chip, and routing lines for re-distributing the signals/and or power transmitted via the TSVs. | 01-03-2013 |
20130032947 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package that stably protects an internal semiconductor chip from external shocks, and a method of manufacturing the semiconductor package is disclosed. The semiconductor package includes a first semiconductor chip including a first body layer having a first surface, a second surface, and a lateral surface between the first surface and the second surface, and a first protective layer that exposes an edge portion of the first surface and forms a step difference with the first surface; an encapsulation structure that covers a lateral surface of the first body layer and the edge portion of the first surface so as to encapsulate the first semiconductor chip to have a locking structure; and a first conductive terminal formed on the first body layer through the protective layer. | 02-07-2013 |
20130134606 | SEMICONDUCTOR PACKAGES - A semiconductor package may include a substrate including a substrate pad on a top surface thereof; at least one semiconductor chip including a connection terminal electrically connected to the substrate on an active surface thereof, and mounted on the substrate; a heat release pattern formed between the substrate and the at least one semiconductor chip and configured to generate heat; and underfill resin underfilled between the substrate and the at least one semiconductor chip and comprising fillers. A semiconductor package may include a substrate including a substrate pad on a top surface thereof and a first heat release pattern configured to generate heat, and a semiconductor chip including a bonding pad formed on an active surface facing the substrate and a second heat release pattern configured to generate heat. | 05-30-2013 |
20130175702 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip. | 07-11-2013 |
20130175706 | SEMICONDUCTOR PACKAGE - A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip. | 07-11-2013 |
20130221493 | SEMICONDUCTOR PACKAGE - Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end. | 08-29-2013 |
20130259092 | SYSTEM AND METHOD FOR PREDICTING THE TEMPERATURE OF A DEVICE - A method of predicting a temperature includes operatively coupling a temperature prediction circuit to a device including a semiconductor chip, determining a correlation between a current and voltage of the temperature prediction circuit, and predicting a temperature with respect to power applied to the device using the determined correlation. | 10-03-2013 |
20140057430 | SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector. | 02-27-2014 |
20140273350 | METHOD OF FABRICATING SEMICONDUCTOR MULTI-CHIP STACK PACKAGES - Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures. | 09-18-2014 |
20140367839 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip. | 12-18-2014 |
20150048493 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability. | 02-19-2015 |