Patent application number | Description | Published |
20100060527 | ELECTROMAGNETIC BAND GAP TUNING USING UNDULATING BRANCHES - Embodiments of the invention include electromagnetic band gap (EBG) structures having undulating branches to tune the resulting stopband. A periodically patterned structure of conductive patches are interconnected by the undulating branches. Physical parameters of the undulating branches, such as the number of undulations or “turns” per branch, may be selected to tune the stopband in an effort to achieve a target stopband. Accordingly, embodiments of the invention also include methods of designing and manufacturing an EBG structure using undulating branches. | 03-11-2010 |
20100073893 | MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE - Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer. | 03-25-2010 |
20100084176 | PRESERVING STOPBAND CHARACTERISTICS OF ELECTROMAGNETIC BANDGAP STRUCTURES IN CIRCUIT BOARDS - The stopband characteristics of an electromagnetic bandgap structure in a printed circuit board may be preserved by selectively forming slots in an additional conductive layer of the printed circuit board. For example, an electromagnetic bandgap structure may include a layer with a continuous conductive region and another layer with a periodically patterned region having a plurality of spaced-apart patches interconnected by branches. Additional conductive layers may be included within the printed circuit board without neutralizing the bandgap by forming slots in the conductive layers in general alignment with spaces between the patches. | 04-08-2010 |
20110073359 | Through-Hole-Vias In Multi-Layer Printed Circuit Boards - Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper. | 03-31-2011 |
20110103030 | Packages and Methods for Mitigating Plating Stub Effects - Packages and methods for mitigating plating stub effects. The semiconductor package includes an interposer substrate having a first side, a second side, a peripheral edge connecting the first side with the second side, a signal line on the first side, and an electrode pad on the first side. A semiconductor element is mounted on the first side of the interposer substrate. The semiconductor element is connected with the electrode pad by the signal line. A terminating resistor is mounted on the interposer substrate. A plating stub, which is located on the interposer substrate, has a first end portion that terminates near the peripheral edge of the interposer substrate and a second end portion that is electrically connected to the electrode. The first end portion is electrically connected through the terminating resistor to an electrical ground. | 05-05-2011 |
20110108948 | INTEGRATED DECOUPLING CAPACITOR EMPLOYING CONDUCTIVE THROUGH-SUBSTRATE VIAS - A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips. | 05-12-2011 |
20110222224 | CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE - A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers. | 09-15-2011 |
20130003335 | CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE - A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers. | 01-03-2013 |
20130008696 | CORLES MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE - A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers. | 01-10-2013 |
20130344675 | INTEGRATED DECOUPLING CAPACITOR EMPLOYING CONDUCTIVE THROUGH-SUBSTRATE VIAS - A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips. | 12-26-2013 |