Patent application number | Description | Published |
20080307642 | METHOD OF MANUFACTURING ELECTRONIC COMPONENT INTEGRATED SUBSTRATE - There are provided the steps of mounting a semiconductor chip on a first substrate, providing an underfill resin between the semiconductor chip and the first substrate, forming a through hole on a second substrate, providing an electrode on the second substrate, bonding the first and second substrates to include the semiconductor chip through the electrode, and filling a sealing resin between the first and second substrates at a filling pressure capable of correcting a warpage generated on the semiconductor chip and the first substrate while discharging air from the through hole. | 12-18-2008 |
20080315413 | ELECTRONIC DEVICE MANUFACTURING METHOD AND ELECTRONIC DEVICE - There are provided the steps of forming a bump | 12-25-2008 |
20100112759 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE EMBEDDED SUBSTRATE - A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a third insulating layer on a surface of each of the semiconductor device and the second insulating layer; a sixth step of mounting a wiring substrate on a surface of each of the semiconductor device and the second insulating layer; a seventh step of forming a via-hole in the second insulating layer and the third insulating layer; and an eighth step of forming a second wiring pattern on a surface of each of the first insulating layer and the second insulating layer. | 05-06-2010 |
20100112802 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE EMBEDDED SUBSTRATE - A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a first wiring pattern on a surface of each of the first insulating layer and the second insulating layer; a sixth step of forming a via-hole from which the first wiring pattern is exposed on the second insulating layer; and a seventh step of forming a second wiring pattern electrically connected on a surface of the second insulating layer. | 05-06-2010 |
20100112804 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE EMBEDDED SUBSTRATE - A manufacturing method for a semiconductor device embedded substrate, includes: a first step including: a step of forming a connection terminal on an electrode pad formed on a semiconductor integrated circuit, a step of forming a first insulating layer on the semiconductor integrated circuit, a step of providing a plate-like body on the first insulating layer, a step of exposing a part of the connection terminal, and a step of removing the plate-like body to manufacture a semiconductor device; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; and a fifth step of forming a first wiring pattern electrically connected to the exposed portion on a surface of each of the first insulating layer and the second insulating layer. | 05-06-2010 |
20110256662 | CHIP EMBEDDED SUBSTRATE AND METHOD OF PRODUCING THE SAME - A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip. | 10-20-2011 |
20120013021 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDCUTOR DEVICE - An electronic component incorporation substrate and a method for manufacturing the same that provide a high degree of freedom for selecting materials. An electronic component incorporation substrate includes a first structure, which has a substrate and an electronic component. The substrate includes a substrate body having first and second surfaces. A first wiring pattern is formed on the first surface and electrically connected to a second wiring pattern formed on the second surface through a through via. The electronic component is electrically connected to the first wiring pattern. The electronic component incorporation substrate includes a sealing resin, which seals the first structure, and a third wiring pattern, which is connected to the second wiring pattern through a second via. | 01-19-2012 |
20130099273 | WIRING SUBSTRATE, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes a substrate, a first insulating layer formed on the substrate, wiring patterns formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer. The second insulating layer covers the wiring patterns and includes a first opening that partially exposes adjacent wiring patterns as a pad. A projection is formed in an outer portion of the substrate located outward from where the first opening is arranged. The projection rises in a thickness direction of the substrate. | 04-25-2013 |
20130113015 | Substrate, Light Emitting Device and Method for Manufacturing Substrate - A substrate includes a first lead frame, a second lead frame, and a resin layer. The first lead frame includes a heat sink and a plurality of electrodes for external connection. The second lead frame is laminated on the first lead frame and includes a plurality of wirings for mounting light emitting elements. The resin layer is filled between the first lead frame and the second lead frame. The plurality of wirings are arranged above the heat sink. The plurality of electrodes and part of the plurality of wirings are joined with each other. | 05-09-2013 |
20140313681 | CHIP EMBEDDED SUBSTRATE AND METHOD OF PRODUCING THE SAME - An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part. | 10-23-2014 |
Patent application number | Description | Published |
20080268582 | Method for Exposing Photo-Sensitive SAM Film and Method for Manufacturing Semiconductor Device - A disclosed technology is a method for exposing a photo-sensitive SAM film, wherein a self-assembled-monolayer (photo-sensitive SAM film) having photo-sensitivity, exhibiting hydrophobicity before exposure, and exhibiting hydrophilicity after exposure is formed on a substrate, exposure is performed to the substrate in a state in which a surface of the substrate on which the film has been formed is dipped in liquid or in a state in which a light-sensitive surface of the substrate faces downward to be in contact with liquid, exposure light is ultraviolet light, visible light, or light with an exposure-wavelength of 350 nm or more to 800 nm or less, and the liquid is at least one of organic solvent containing an aromatic group and organic solvent of alcohols, ethers, or ketones. | 10-30-2008 |
20080315191 | Organic Thin Film Transistor Array and Method of Manufacturing the Same - An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and insulator. At this time, in order to configure a predetermined circuit, the process is performed, as a source electrode and a drain electrode of the p-type TFT and a source electrode and a drain electrode of the n-type TFT being connected all, respectively, and an unnecessary interconnection is cut by irradiating light using a scanning laser exposure apparatus or the like. | 12-25-2008 |
20090001361 | Thin-film transistor device and a method for manufacturing the same - The present invention provides a method of manufacturing a thin-film transistor device. This method enables improvement in performance of a complementary TFT circuit incorporated in a thin- and light-weighted image display device or a flexible electronic device and also enables reduction of power consumption and reduction of manufacturing cost of the circuit. Further in the method, the number of manufacturing steps is decreased so that mass production and growth in size of thin film transistor devices are facilitated through a printing technique. In this method, electrodes forming n-type and p-type TFT and an organic semiconductor are made of the same material in both types of TFT by the solution-process and/or printable process method. A first polarizable thin-film | 01-01-2009 |
20090114958 | Wiring Board and Method for manufacturing the Same - A wiring board with an electronic device comprising a plurality of trenches arranged in parallel on a substrate, a common trench communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the plurality of trenches, and an electrode layer connected with the metal layer and formed on a bottom of the common trench, wherein the electrode layer on the bottom of the common trench constitutes a source electrode or a drain electrode of a field effect transistor, whereby the wiring board and an electronic circuit having a good fine wire pattern and a good narrow gap between the patterns using a coating material can be formed, and a reduction for a cost of an organic thin film electronic device and the electronic circuit can be attained since they can be realized through a development of a printing technique. | 05-07-2009 |
20090215222 | Manufacturing method of semiconductor device - When a thin film transistor is manufactured by using a printing method, the precision of alignment between a first electrode and a second electrode becomes a problem. If it is manufactured by using photolithography, a photomask for each layer is necessary, resulting in the cost being increased. The essence of the present invention is that not only processing the gate shape is carried out over the substrate by using a resist pattern formed by exposing using a photo-mask for the gate pattern but also processing the source-drain electrodes is carried out by lifting-off. As a result, alignment between the source-drain electrode and the gate electrode is carried out. | 08-27-2009 |
20090294852 | Electronic device - A thin-film transistor includes an insulating substrate, a source electrode, and a drain electrode, disposed over the top of the insulating substrate, a semiconductor layer electrically continuous with the source electrode, and the drain electrode, respectively, a gate dielectric film formed over the top of at least the semiconductor layer; and a gate electrode disposed over the top of the gate dielectric film so as to overlap the semiconductor layer. Further, a first bank insulator is formed so as to overlie the source electrode, a second bank insulator is formed so as to overlie the drain electrode, and the semiconductor layer, the gate dielectric film, and the gate electrode are embedded in a region between the first bank insulator, and the second bank insulator. | 12-03-2009 |
20100033695 | LITHOGRAPHY APPARATUS AND MANUFACTURING METHOD USING THE SAME - An lithography apparatus for manufacturing an organic transistor that is capable of aligning accurately in self-alignment fashion relative positions of a gate electrode and a pair of source and drain electrodes and has high productivity. In an lithography apparatus for radiating a light to a photosensitive self-assembled film and exposing the same in self-aligning fashion using a gate electrode as a mask, by transporting a flexible translucent substrate from roller to roller and forming a gate electrode, an insulating layer, and the photosensitive self-assembled film on the flexible substrate when an organic transistor is formed on the flexible substrate, a reflection preventing film is provided on an inner wall of the apparatus that is on the opposite side of the flexible substrate as seen from an exposure light source. | 02-11-2010 |
Patent application number | Description | Published |
20090008765 | CHIP EMBEDDED SUBSTRATE AND METHOD OF PRODUCING THE SAME - A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip. | 01-08-2009 |
20090145636 | ELECTRONIC COMPONENT MOUNTING PACKAGE - An electronic component mounting package includes a structure (coreless substrate) in which a plurality of wiring layers are stacked one on top of another with insulating layers interposed therebetween and are interconnected through via holes formed in the insulating layers. The entire surface of the coreless substrate, exclusive of pad portions defined at desired positions of the outermost wiring layers thereof, is covered with a molding resin. Further, an interposer is mounted on the side of the electronic component mounting surface of the coreless substrate, and the molding resin is partially filled into a gap between the coreless substrate and the interposer. | 06-11-2009 |
20090250803 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a chip, a laminated wiring structure formed integrally with the chip, a frame disposed to surround the chip and made of a material having stiffness, and a sealing resin formed to bury therein the frame and at least the periphery of the side surface of the chip. The laminated wiring structure includes a required number of wiring layers, which are formed by patterning in such a manner that a wiring pattern directly routed from an electrode terminal of the chip is electrically connected to pad portions for bonding external connection terminals, the pad portions being provided, at a position directly below a mounting area of the chip and at a position directly below an area outside the mounting area, on a surface to which the external connection terminals are bonded. | 10-08-2009 |
20100025081 | WIRING SUBSTRATE AND ELECTRONIC COMPONENT DEVICE - A wiring substrate includes a frame-shaped reinforcing plate in which an opening portion is provided in a center portion, an interposer arranged in the opening portion of the reinforcing plate and having such a structure that a wiring layer connected mutually via a through electrode is formed on both surface sides of a substrate respectively, a resin portion filled between a side surface of the interposer and a side surface of the opening portion of the reinforcing plate, and coupling the interposer and the reinforcing plate, and an n-layered (n is an integer of 1 or more) lower wiring layer connected the wiring layer on the lower surface side of the interposer to extend from the interposer to an outer area. | 02-04-2010 |
20110133342 | WIRING BOARD, MANUFACTURING METHOD OF THE WIRING BOARD, AND SEMICONDUCTOR PACKAGE - A wiring board includes a ceramic substrate including a plurality of stacked ceramic layers, an internal wiring, and an electrode, the internal wiring being electrically connected to the electrode, the electrode being exposed from a first surface of the ceramic substrate; and a silicon substrate including a wiring layer, the wiring layer including a wiring pattern and a via-fill, the wiring pattern being formed on a main surface of the silicon substrate, an end of the via-fill being electrically connected to the wiring pattern, another end of the via-fill being exposed from a rear surface of the silicon substrate positioned opposite to the main surface, wherein the rear surface of the silicon substrate is anodically bonded to the first surface of the ceramic substrate; and the via-fill of the silicon substrate is directly connected to the electrode of the ceramic substrate. | 06-09-2011 |
20110169133 | WIRING SUBSTRATE, METHOD FOR MANUFACTURING WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE INCLUDING WIRING SUBSTRATE - A wiring substrate includes a ceramic substrate including plural ceramic layers, an inner wiring, and an electrode electrically connected to the inner wiring, the electrode exposed on a first surface of the ceramic substrate, and a silicon substrate body having a front surface and a back surface situated on an opposite side of the front surface and including a wiring pattern formed on the front surface and a via filling material having one end electrically connected to the wiring pattern and another end exposed at the back surface. The back surface is bonded to the first surface of the ceramic substrate via a polymer layer. The via filling material penetrates through the polymer layer and is directly bonded to the electrode. | 07-14-2011 |
20110180930 | WIRING BOARD, MANUFACTURING METHOD OF THE WIRING BOARD, AND SEMICONDUCTOR PACKAGE - A wiring board includes a ceramic substrate including a plurality of stacked ceramic layers, an internal wiring, and an electrode electrically connected to the internal wiring, the electrode being exposed from a first surface of the ceramic substrate; and a silicon substrate including a wiring layer, the wiring layer including a wiring pattern and a via-fill, the wiring pattern being formed on a main surface of the silicon substrate, an end of the via-fill being electrically connected to the wiring pattern, another end of the via-fill being exposed from a rear surface of the silicon substrate positioned opposite to the main surface, wherein the another end of the via-fill is bonded to the electrode of the ceramic substrate via a metal layer. | 07-28-2011 |
20120074578 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT MOUNTED BOARD, AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A semiconductor element includes connection terminals. The connection terminals are each shaped in such a manner that the transverse cross-sectional area in a portion near the leading end thereof decreases toward the leading end. Specifically, the shape of each of the connection terminals is columnar except for the portion near the leading end, and the side surface in the portion near the leading end of the connection terminal is shaped in a tapered form. Furthermore, a metal layer for improving a solder wettability may be formed at least on the side surface shaped in the tapered form, of the connection terminal. | 03-29-2012 |
20120103663 | WIRING SUBSTRATE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes a heat sink to dissipate heat generated in an electronic part mounted in an electronic part loading area on a principal surface of the wiring substrate, an encapsulation resin to cover the heat sink, an inner connection terminal having an end face electrically connected to an electrode of the electronic part, and an outer connection terminal electrically connected to the inner connection terminal via a wiring and having an end face for inputting and outputting of a signal with an external device. The encapsulation resin is arranged to cover a part of the wiring, the inner connection terminal except the end face, and the outer connection terminal except the end face. A surface of the heat sink, the end face of the inner connection terminal, and the end face of the outer connection terminal are flush with and exposed to the principal surface. | 05-03-2012 |
20130126916 | PACKAGE FOR MOUNTING ELECTRONIC COMPONENTS, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING THE PACKAGE - A package includes: a leadframe made of conductive material and on which the plurality of electronic components are to be mounted, the leadframe including a first surface and a second surface opposite to the first surface and including a plurality of elongate portions arranged in parallel to each other with a gap interposed between the adjacent elongate portions; a heat sink including a first surface and a second surface opposite to the first surface, wherein the leadframe is disposed above the heat sink such that the second surface of the leadframe faces the first surface of the heat sink; and a resin portion, wherein the leadframe and the heat sink are embedded in the resin portion such that the first surface of the leadframe and the second surface of the heat sink are exposed from the resin portion, respectively. | 05-23-2013 |
20130153945 | LIGHT-EMITTING ELEMENT MOUNTING PACKAGE, LIGHT-EMITTING ELEMENT PACKAGE, AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a light-emitting element mounting package including laminating a metallic layer on an insulating layer; forming a light-emitting element mounting area which includes a pair of electroplating films formed by electroplating using the metallic layer as a power supply layer on the metallic layer; forming a light-emitting element mounting portion in which a plurality of wiring portions are separated by predetermined gaps, by removing predetermined portions of the metallic layer, wherein, in the forming the light-emitting element mounting portion, the metallic layer is removed so that one of the pair of electroplating films belongs to one wiring portion of the plurality of wiring portions and another of the pair of electroplating films belongs to another wiring portion adjacent to the one wiring portion. | 06-20-2013 |
Patent application number | Description | Published |
20080259307 | EXPOSURE APPARATUS AND DEVICE MANUFACTURING METHOD - A scanning exposure apparatus which exposes a substrate is disclosed. The apparatus comprises an illumination system configured to illuminate an illumination region of an original, a projection optical system configured to project a pattern of the original onto the substrate, and a stop configured to shield a flare generating component of flare light which travels from the projection optical system to the substrate, and to pass the remaining component of the flare light. An aperture of the stop has a shape different from a shape of the illumination region, and the aperture of the stop includes a portion whose dimension in a first direction parallel to a scanning direction of the substrate changes in accordance with a distance from the center of the aperture in a second direction perpendicular to the first direction. | 10-23-2008 |
20090180093 | EVALUATION METHOD, CONTROL METHOD, EXPOSURE APPARATUS, AND MEMORY MEDIUM - A method of evaluating an imaging performance of a projection optical system, comprising a step of specifying a polarization change of the projection optical system, which represents a relationship between a polarization state of light impinging on the projection optical system and the polarization state of the light exiting from the projection optical system, a first calculation step of calculating a value of a parameter having a correlation with the polarization change of the projection optical system specified in the specifying step, and a second calculation step of calculating an index value representing the imaging performance in a state that the projection optical system has the polarization change specified in the specifying step, based on an amount of change in the index value representing the imaging performance upon changing the value of the parameter by a unit amount, and the value of the parameter calculated in the first calculation step. | 07-16-2009 |
20090201480 | EVALUATION METHOD, ADJUSTMENT METHOD, EXPOSURE APPARATUS, AND MEMORY MEDIUM - A method evaluating an imaging performance of a projection optical system according to a polarization state of light in a pupil of an illumination optical system for an exposure apparatus, comprises a representation step of numerically representing the polarization state in the pupil of the illumination optical system, an assumption step of virtually dividing the pupil of the illumination optical system into a plurality of partial regions, each of which includes a light incident region and a light non-incident region, and assuming individual polarization states for the plurality of partial regions so that one polarization state is assumed for the whole of each partial region based on the polarization state numerically represented in the representation step; and a calculation step of calculating the imaging performance of the projection optical system under a condition in which the plurality of partial regions have the polarization states individually assumed in the assumption step. | 08-13-2009 |
20120096413 | PROGRAM STORAGE MEDIUM AND METHOD FOR DETERMINING EXPOSURE CONDITION AND MASK PATTERN - A method of determining an exposure condition and a mask pattern includes: setting the exposure condition and the mask pattern; temporarily determining the mask pattern using a first evaluation function describing indices of quality of an image of the mask pattern, using the set exposure condition; calculating a value of a second evaluation function describing indices of quality of the image of the mask pattern, using the temporarily determined mask pattern and the set exposure condition; changing the exposure condition and the mask pattern based on the value of the calculated second evaluation function; and judging whether to execute a process of repeating the temporarily determining step and the calculating step. In the judging step, the mask pattern temporarily determined in the latest second step, and the exposure condition changed in the latest fourth step are determined as the mask pattern and the exposure condition, respectively. | 04-19-2012 |
20130246982 | GENERATION METHOD, STORAGE MEDIUM, AND INFORMATION PROCESSING APPARATUS - The present invention provides a generation method of generating data for a mask pattern to be used for an exposure apparatus including a projection optical system for projecting a mask pattern including a main pattern and auxiliary pattern onto a substrate, including a step of setting a generation condition under which the auxiliary pattern is generated, and a step of determining whether a value of an evaluation function describing an index which indicates a quality of an image of the mask pattern calculated, wherein if it is determined that the value of the evaluation function falls outside a tolerance range, the generation condition is changed to set a new generation condition. | 09-19-2013 |
20130268902 | DECISION METHOD, STORAGE MEDIUM AND INFORMATION PROCESSING APPARATUS - The present invention provides a decision method which decides a mask pattern used in an exposure apparatus comprising a projection optical system that projects a mask pattern including a main pattern and an auxiliary pattern onto a substrate, and an exposure condition in the exposure apparatus, the method including a step of calculating an image of a mask pattern formed on the substrate by the projection optical system while changing settings of the mask pattern and the exposure condition, and deciding the mask pattern and the exposure condition based on the image of the mask pattern, wherein the step includes determining whether or not to generate a new auxiliary pattern after the settings are changed. | 10-10-2013 |
20130321789 | MASK DATA GENERATION METHOD - A mask data generation method includes obtaining data of a pattern including a plurality of pattern elements, dividing a region of the pattern into a plurality of sections so that each pattern element is arranged in each section by using the obtained data of the pattern and generating map data including information indicative of presence or absence of the pattern element in each section, setting one piece of mask individual information out of a plurality pieces of mask individual information for each section including the pattern element by using a constraint condition, which inhibits setting of same mask individual information in a constraint region including one section and surrounding sections thereof, and the map data, and generating the data of the plurality of masks corresponding to the plurality pieces of mask individual information by using the set mask individual information. | 12-05-2013 |
20130329202 | PATTERN GENERATION METHOD - A pattern generation method for generating a pattern of a cell used to generate a pattern of a mask using a computer, includes obtaining data of pattern of the cell, calculating image of the pattern of the cell to obtain an evaluation value of the image by repeatedly changing a parameter value of an exposure condition when the mask which has the pattern of the cell is illuminated to project image of the pattern of the cell onto a substrate to expose the substrate, and a parameter value of the pattern of the cell, and determining parameter value of the pattern of the cell when the evaluation value satisfies a predetermined evaluation standard. | 12-12-2013 |
20140080041 | METHOD FOR CREATING MASK DATA, PROGRAM, INFORMATION PROCESSING APPARATUS, AND METHOD FOR MANUFACTURING MASK - Data regarding a first corrected patterns on a single cell corrected such that an evaluation value of a pattern formed on a substrate after an image of a pattern of the single cell is projected onto a resist on the substrate and the resist is developed is obtained for each of a plurality of cells, a first evaluation value obtained by evaluating a projected image of the first corrected pattern on the single cell generated by the projection system is obtained for each of the cells, a second evaluation value obtained by, when the cells are arranged adjacent to one another, evaluating the projected images of the first corrected patterns on the cells is calculated, and creating a second corrected pattern by correcting the first corrected patterns on the cells arranged adjacent to one another such that the second evaluation value becomes close to the first evaluation value. | 03-20-2014 |
20140245241 | GENERATION METHOD, STORAGE MEDIUM AND INFORMATION PROCESSING APPARATUS - The present invention provides a generation method of generating data of patterns of a plurality of masks used in an exposure apparatus for exposing a substrate, including a step of specifying, from a plurality of points on a grid having pattern elements to be formed on the substrate as intersections, an allowable point that allows a pattern to be transferred other than points of target pattern elements constituting a target pattern to be formed on the substrate, and a step of, for a pattern element group including a target pattern element whose distance to an adjacent target pattern element is shorter than a resolution limit of the exposure apparatus, grouping the adjacent target pattern elements on the grid a space between which is filled with the allowable point. | 08-28-2014 |
Patent application number | Description | Published |
20150177609 | METHOD FOR EVALUATING OPTICAL IMAGE OF PATTERN, RECORDING MEDIUM, AND INFORMATION PROCESSING APPARATUS - A method being performed by a processor includes, acquiring data of patterns of a plurality of cells that include an identified pattern for which an evaluation value of an optical image falls outside a first allowable range among patterns in which each a pattern being single cell alone, creating the pattern of a mask by arranging the patterns of the plurality of cells that include the identified pattern, and evaluating an optical image of the identified pattern in the created pattern of the mask. | 06-25-2015 |
20150178431 | MASK PATTERN GENERATION METHOD - A method for generating a pattern of a mask includes obtaining data of a plurality of polygons representing a plurality of pattern elements, grouping polygons which overlap or contact with each other among the plural polygons in one group, not setting an evaluation position for evaluating an image of a pattern of the one group on a line segment of sides which overlap or contact with each other among sides of the polygon of the one group, and setting an evaluation position at a portion except for the line segment, and repeating calculating the image of the pattern of the one group, evaluating the calculated image at the set evaluation position, and correcting the pattern based on a result of the evaluating, and generating the pattern of the mask based on a result of the repeating step. | 06-25-2015 |
20150213175 | MASK DATA GENERATING METHOD, STORAGE MEDIUM STORING COMPUTER PROGRAM AND INFORMATION PROCESSING APPARATUS FOR EXECUTION OF THE SAME - A mask data generating method for generating data of a plurality of masks used in a plurality of exposures in which exposure light is irradiated onto a substrate using a mask, and then exposure light is irradiated onto the substrate using another mask. The method includes the steps of obtaining data for a pattern including a plurality of pattern elements, determining formulation of a disposition limitation condition for the pattern elements, analyzing the distance between the pattern elements, determining formulation of the distance limitation condition, and applying a first variable configured to express a number of pattern divisions and a second variable configured to express a distance related to all pattern elements in a cost function and thereby dividing the pattern. | 07-30-2015 |
20150356214 | OPERATION METHOD AND APPARATUS FOR PERFORMING LITHOGRAPHY-RELATED SIMULATION, AND RECORDING MEDIUM - A sub processing unit, which is easy in design and versatile, is used to perform a lithography-related simulation at high speed. An operation method for performing a lithography-related simulation for forming a pattern on a substrate by using a processor includes sharing the lithography-related simulations with a central processing unit and a Many Integrated Core. Among the lithography-related simulations, the Many Integrated Core performs a parallel operation related to data of a spatial domain. | 12-10-2015 |
20160026743 | METHOD FOR GENERATING PATTERN, STORAGE MEDIUM, AND INFORMATION PROCESSING APPARATUS - A method for generating a pattern includes defining a footprint of a main pattern in each cell, arranging a first cell and a second cell which has an auxiliary pattern outside the footprint of the main pattern, side by side in such a manner that the auxiliary pattern outside the footprint of the second cell is present in the footprint of the main pattern of the first cell, and generating the pattern of the mask by removing a pattern element of the auxiliary pattern outside the footprint of the second cell in a portion where the pattern element of the auxiliary pattern outside the footprint of the second cell is close to or overlaps with the main pattern in the first cell of the first cell and the second cell arranged side by side. | 01-28-2016 |
20160035628 | PATTERN FORMATION METHOD - The present invention provides a pattern formation method of forming a pattern on a substrate by partially removing a line and space pattern formed on the substrate, comprising a first formation step of forming a first layer including a plurality of first openings on the line and space pattern, a second step of forming, on the first layer, a second layer including a second opening for exposing one or more first openings, which are used to partially remove the line and space pattern, among the plurality of first openings, and a removing step of partially removing the line and space pattern through the second opening and the first opening, wherein the plurality of first openings are located on a plurality of lines of the line and space pattern. | 02-04-2016 |