Patent application number | Description | Published |
20110012197 | METHOD OF FABRICATING TRANSISTORS AND A TRANSISTOR STRUCTURE FOR IMPROVING SHORT CHANNEL EFFECT AND DRAIN INDUCED BARRIER LOWERING - A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively. | 01-20-2011 |
20120045880 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate. | 02-23-2012 |
20120070948 | ADJUSTING METHOD OF CHANNEL STRESS - An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region. | 03-22-2012 |
20120086054 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties. | 04-12-2012 |
20120196418 | METHOD OF FABRICATING TRANSISTORS - A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively. | 08-02-2012 |
20120199890 | TRANSISTOR STRUCTURE - A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer. | 08-09-2012 |
20120309158 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer. | 12-06-2012 |
20130119479 | TRANSISTOR STRUCTURE - A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer. | 05-16-2013 |