Patent application number | Description | Published |
20130277719 | Gate Electrodes with Notches and Methods for Forming the Same - A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region. | 10-24-2013 |
20130277785 | Methods and Apparatus for Glass Removal in CMOS Image Sensors - Methods for glass removal while forming CMOS image sensors. A method for forming a device is provided that includes forming a plurality of pixel arrays on a device wafer; bonding a carrier wafer to a first side of the device wafer; bonding a substrate over a second side of the device wafer; thinning the carrier wafer; forming electrical connections to the first side of the device wafer; subsequently de-bonding the substrate from the second side of the device wafer; and subsequently singulating individuals ones of the plurality of pixel arrays from the device wafer. An apparatus is disclosed. | 10-24-2013 |
20130277789 | Methods and Apparatus for Via Last Through-Vias - Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer. | 10-24-2013 |
20130284885 | Method and Apparatus for Image Sensor Packaging - Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond bad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding between the sensor and the ASIC. | 10-31-2013 |
20130285180 | Apparatus for Vertically Integrated Backside Illuminated Image Sensors - A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias. | 10-31-2013 |
20130292750 | IMAGE DEVICE AND METHODS OF FORMING THE SAME - A method of forming of an image sensor device includes an isolation well formed in a pixel region of a substrate. The isolation well has a first conductivity type. A gate stack is formed over the isolation well on the substrate. A mask layer is formed over the isolation well and covering at least a majority portion of the gate stack. A plurality of dopants is implanted in the pixel region, using the gate stack and the mask layer as masks, to form doped isolation features. The plurality of dopants has the first conductivity type. A source region and a drain region are formed on opposite sides of the gate stack in the substrate. The source region and the drain region have a second conductivity type opposite to the A conductivity. | 11-07-2013 |
20130307103 | Vertically Integrated Image Sensor Chips and Methods for Forming the Same - A device includes a Backside Illumination (BSI) image sensor chip, which includes an image sensor disposed on a front side of a first semiconductor substrate, and a first interconnect structure including a plurality of metal layers on the front side of the first semiconductor substrate. A device chip is bonded to the image sensor chip. The device chip includes an active device on a front side of a second semiconductor substrate, and a second interconnect structure including a plurality of metal layers on the front side of the second semiconductor substrate. A first via penetrates through the BSI image sensor chip to connect to a first metal pad in the second interconnect structure. A second via penetrates through a dielectric layer in the first interconnect structure to connect to a second metal pad in the first interconnect structure, wherein the first via and the second via are electrically connected. | 11-21-2013 |
20130320194 | Image Sensors with a High Fill-Factor - A device includes a first chip including an image sensor therein, and a second chip bonded to the first chip. The second chip includes a logic device selected from the group consisting essentially of a reset transistor, a selector, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. | 12-05-2013 |
20130334638 | Apparatus and Method for Backside Illuminated Image Sensors - A backside illuminated image sensor comprises a photodiode and a first transistor located in a first substrate, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a plurality of logic circuits formed in a second substrate, wherein the second substrate is stacked on the first substrate and the logic circuit are coupled to the first transistor through a plurality of bonding pads. | 12-19-2013 |
20140015084 | Method and Apparatus for Image Sensor Packaging - Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together. | 01-16-2014 |
20140035082 | Elevated Photodiodes with Crosstalk Isolation - A device includes a plurality of isolation spacers, and a plurality of bottom electrodes, wherein adjacent ones of the plurality of bottom electrodes are insulated from each other by respective ones of the plurality of isolation spacers. A plurality of photoelectrical conversion regions overlaps the plurality of bottom electrodes, wherein adjacent ones of the plurality of photoelectrical conversion regions are insulated from each other by respective ones of the plurality of isolation spacers. A top electrode overlies the plurality of photoelectrical conversion regions and the plurality of isolation spacers. | 02-06-2014 |
20140035083 | Elevated Photodiode with a Stacked Scheme - A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode. | 02-06-2014 |
20140042298 | CMOS Image Sensor Chips with Stacked Scheme and Methods for Forming the Same - A device includes an image sensor chip having an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip, wherein the read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip, wherein the peripheral circuit chip includes a logic circuit. | 02-13-2014 |
20140042299 | CMOS Image Sensor Chips with Stacked Scheme and Methods for Forming the Same - A device includes an image sensor chip including an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip. The read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip. The peripheral circuit chip includes a logic circuit, a through via penetrating through a semiconductor substrate of the peripheral circuit chip, and an electrical connector at a bottom surface of the peripheral circuit chip. The electrical connector is electrically coupled to the logic circuit in the peripheral circuit chip through the through via. | 02-13-2014 |
20140113398 | Apparatus for Vertically Integrated Backside Illuminated Image Sensors - A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias. | 04-24-2014 |
20140117546 | HYBRID BONDING MECHANISMS FOR SEMICONDUCTOR WAFERS - The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers. | 05-01-2014 |
20140193940 | Method and Apparatus for Image Sensor Packaging - Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together. | 07-10-2014 |
20140231887 | Method and Apparatus for Image Sensor Packaging - A backside illuminated image sensor comprises a photodiode and a first transistor in a sensor region and located in a first substrate, wherein the first transistor is electrically coupled to the photodiode. The image sensor further comprises a plurality of logic circuits formed in a second substrate, wherein the second substrate is stacked on the first substrate and the logic circuit are coupled to the first transistor through a plurality of bonding pads, the bonding pads disposed outside of the sensor region. | 08-21-2014 |
20140264698 | Image Sensor Device and Method - A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration. | 09-18-2014 |
20140264947 | Interconnect Apparatus and Method - A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask. | 09-18-2014 |
20140308772 | Vertically Integrated Image Sensor Chips and Methods for Forming the Same - A method includes bonding a Backside Illumination (BSI) image sensor chip to a device chip, forming a first via in the BSI image sensor chip to connect to a first integrated circuit device in the BSI image sensor chip, forming a second via penetrating through the BSI image sensor chip to connect to a second integrated circuit device in the device chip, and forming a metal pad to connect the first via to the second via. | 10-16-2014 |
20150028403 | Semiconductor Switching Device Separated by Device Isolation - A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure. | 01-29-2015 |
20150041945 | PICKUP DEVICE STRUCTURE WITHIN A DEVICE ISOLATION REGION - A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region. | 02-12-2015 |
20150060963 | IMAGE SENSOR DEVICE - An image sensor device comprises an isolation well region within a substrate. A gate stack is over the isolation well region on the first surface of the substrate. The gate stack has an edge. A doped isolation feature is within the substrate between the isolation well region and the gate stack. The doped isolation feature surrounds an active area. The gate stack is over the active area. The doped isolation feature extends from the edge of the gate stack under the gate stack. | 03-05-2015 |
20150064832 | Elevated Photodiode with a Stacked Scheme - A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode. | 03-05-2015 |
20150079718 | Image Sensors with a High Fill-Factor - A device includes a first chip including an image sensor therein, and a second chip bonded to the first chip. The second chip includes a logic device selected from the group consisting essentially of a reset transistor, a selector, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. | 03-19-2015 |