Patent application number | Description | Published |
20080251871 | Semiconductor fabrication method and system - Embodiments of the present invention are generally directed to a method for manufacturing a semiconductor device. In one embodiment, the method includes providing a substrate that includes a via or interconnect. In this embodiment, the method also includes forming a sealed array, in which forming such an array includes attaching a carrier to a first surface of the substrate to form a sealed cavity between the carrier and the substrate. Further, the method of this embodiment also includes forming a redistribution layer on the sealed array over a second surface of the substrate. Devices and systems having a carrier attached to a substrate are also disclosed. | 10-16-2008 |
20080299770 | METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH - A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias. | 12-04-2008 |
20090017576 | Semiconductor Processing Methods - Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening. | 01-15-2009 |
20090215263 | METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH - A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias. | 08-27-2009 |
20090250821 | CORROSION RESISTANT VIA CONNECTIONS IN SEMICONDUCTOR SUBSTRATES AND METHODS OF MAKING SAME - Devices and methods for protecting the metal within a via in a semiconductor substrate from corrosion are provided. Specifically, embodiments of the present invention relate to disposing a corrosion resistant metal layer within a recess formed in a semiconductor substrate such that the metal subsequently deposited within the via will adhere to the corrosion resistant metal layer, then backgrinding the bottom surface of the semiconductor substrate to expose the corrosion resistant metal. For example, the metal deposited within the recess may be copper, while the corrosion resistant metal may be a noble metal such as palladium. | 10-08-2009 |
20090321863 | Method and apparatus providing an imager module with a permanent carrier - Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer. | 12-31-2009 |
20100065970 | MICROFEATURE WORKPIECES HAVING CONDUCTIVE INTERCONNECT STRUCTURES FORMED BY CHEMICALLY REACTIVE PROCESSES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide. | 03-18-2010 |
20100244172 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING PATTERNED RADIATION BLOCKING ON A SEMICONDUCTOR DEVICE - Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer. | 09-30-2010 |
20100315533 | SEMICONDUCTOR FABRICATION METHOD AND SYSTEM - A semiconductor device is disclosed. In one embodiment, a device includes a substrate having one or more vias and a carrier coupled to the substrate to form a sealed cavity between the carrier and the substrate. In some embodiments, the sealed cavity may be pressurized. The device may also include a redistribution layer formed over the one or more vias on a side of the substrate. Other devices, systems, and methods are also disclosed. | 12-16-2010 |
20100323469 | METHODS FOR SEPARATING INDIVIDUAL SEMICONDUCTOR DEVICES FROM A CARRIER - A wafer of integrated circuits may be bonded to a carrier wafer using a layer of bonding material. The thickness of the wafer of integrated circuits may then be reduced using a series of grinding operations. After grinding, backside processing operations may be performed to form scribe channels that separate the die from each other and to form through-wafer vias. The scribe channels may be formed by dry etching and may have rectangular shapes, circular shapes, or other shapes. A pick and place tool may have a heated head. The bonding layer material may be based on a thermoplastic or other material that can be released by application of heat by the heated head of the pick and place tool. The pick and place tool may individually debond each of the integrated circuits from the carrier wafer and may mount the debonded circuits in packages. | 12-23-2010 |
20110070679 | Semiconductor Processing Methods - Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening. | 03-24-2011 |
20110204462 | METHOD AND APPARATUS PROVIDING AN IMAGER MODULE WITH A PERMANENT CARRIER - Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer. | 08-25-2011 |
20110221023 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING PATTERNED RADIATION BLOCKING ON A SEMICONDUCTOR DEVICE - Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer. | 09-15-2011 |
20110230007 | SEMICONDUCTOR FABRICATION METHOD AND SYSTEM - A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method includes attaching a carrier to a substrate including a via to form a pressurized sealed cavity between the carrier and the substrate. The method may also include thinning the substrate attached to the carrier and forming a redistribution layer on the thinned substrate in electrical communication with the via, the redistribution layer including a conductive layer formed through atmospheric pressure chemical vapor deposition. Additional methods, devices, and systems are devices, systems, and methods are also disclosed. | 09-22-2011 |
20110256711 | MICROFEATURE WORKPIECES HAVING CONDUCTIVE INTERCONNECT STRUCTURES FORMED BY CHEMICALLY REACTIVE PROCESSES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide. | 10-20-2011 |
20120061786 | ISOLATED BOND PAD WITH CONDUCTIVE VIA INTERCONNECT - An integrated circuit for use, for example, in a backside illuminated imager device includes circuitry provided on a first side of a substrate, a first conductive pad connected to the circuitry and spaced from the first side of the substrate, a second conductive pad spaced from a second side of the substrate, an electrically conductive interconnect formed through the substrate to interconnect the first and second conductive pads, and a dielectric surrounding the second conductive pad and at least a portion of the interconnect. Methods of forming the integrated circuit are also described. | 03-15-2012 |
20120193741 | METHODS FOR FORMING BACKSIDE ILLUMINATED IMAGE SENSORS WITH FRONT SIDE METAL REDISTRIBUTION LAYERS - Methods for forming backside illuminated (BSI) image sensors having metal redistribution layers (RDL) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a BSI image sensor with RDL and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the BSI image sensor. In another embodiment, a BSI image sensor with RDL and solder bumps may be formed using a permanent carrier during manufacture that partially remains in the completed BSI image sensor. A BSI image sensor may be formed before formation of a redistribution layer on the front side of the BSI image sensor. A redistribution layer may, alternatively, be formed on the front side of an image wafer before formation of BSI components such as microlenses and color filters on the back side of the image wafer. | 08-02-2012 |
20120193744 | IMAGERS WITH BURIED METAL TRENCHES AND THOUGH-SILICON VIAS - An imaging system may include an imager with frontside components such as imaging pixels and backside components. The backside components may include at least a first redistribution layer having metal trenches and through-silicon vias (TSVs) that couple at least some of the backside components to the frontside components. The metal trenches and through-silicon vias may be formed simultaneously. The through-silicon vias may have a width greater than the width of the metal trenches. The greater width of the through-silicon vias may facilitate forming the through-silicon vias simultaneously with the metal trenches. | 08-02-2012 |
20120194669 | FLUID SAMPLE ANALYSIS SYSTEMS - A fluid sample analyzing system may be formed from an image sensor integrated circuit substrate. A glass wafer may be used to cover a wafer of image sensors. The glass wafer and the image sensor wafer may be attached using oxide bonding. Fluid channels may be formed in a layer that is interposed between the image sensor wafer and the glass wafer. The layer may be deposited on the image sensor wafer and the glass wafer prior to oxide bonding. A spacer may be used to deliver the fluid channel layer to the image sensor wafer before the glass wafer is bonded to the image sensor wafer. The spacer may be formed from a silicon wafer. The silicon wafer may be bonded to the image sensor wafer and thinned, leaving a thin spacer wafer layer on the image sensor wafer in which fluid channels may be formed. | 08-02-2012 |
20120194719 | IMAGE SENSOR UNITS WITH STACKED IMAGE SENSORS AND IMAGE PROCESSORS - An image sensor unit has stacked imager and processor integrated circuits. The imager may have an image sensor pixel array on its front surface. Processor die may be mounted back-to-back with respective imagers on a wafer. A photodefinable dielectric film may cover the rear surface of the wafer. Metal traces in the photodefinable dielectric and through-silicon vias in each imager may be used to interconnect the processing circuitry on the front surface of a processor to the image sensor pixel array on the front surface of the imager. Openings may be formed in the photo definable dielectric to allow solder balls to form electrical connections with the metal traces. A cavity may be formed in a photo definable dielectric layer or an imager to accommodate the processor. The processor may also be mounted in a cavity in a separate silicon standoff structure before attaching the standoff structure to the imager. | 08-02-2012 |
20120200749 | IMAGERS WITH STRUCTURES FOR NEAR FIELD IMAGING - An imaging system may include an image sensor configured to image materials at near field imaging ranges from the image sensor. Near field imaging ranges may be on the scale of 1-10 pixel sizes from the image sensor. The materials being imaged may be fluorescent materials that emit radiation at fluorescent wavelengths when the materials are exposed to radiation at excitation wavelengths. The image sensor may include color filter materials that block radiation at excitation wavelengths while transmitting radiation at fluorescent wavelengths. The image sensor may include light guides that reduce cross-talk between pixels and improve localization of emitted radiation, thereby allowing the image sensor to determine which pixel(s) is (are) located beneath the materials being imaged. The light guides may include may include sloped sidewalls and may include reflective sidewalls, which may improve radiation collection (e.g., efficiency) and localization of emitted radiation. | 08-09-2012 |
20120252153 | Semiconductor Processing Methods - Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening. | 10-04-2012 |
20130280851 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING PATTERNED RADIATION BLOCKING ON A SEMICONDUCTOR DEVICE - Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer. | 10-24-2013 |
20130293751 | IMAGING SYSTEMS WITH SEPARATED COLOR FILTER ELEMENTS - An image sensor may be provided with an array of imaging pixels. A color filter array may be formed over photosensitive elements in the pixel array. The color filter array may include a Bayer color filter array. Separating material may be interposed between color filter elements of adjacent imaging pixels. The separating material may be relatively low index of refraction material configured to reduce or eliminate optical crosstalk between adjacent imaging pixels. The separating material may be air so that neighboring color filter elements are separated by an air gap. The air gaps may be formed during the color filter array fabrication process by depositing a sacrificial layer on the substrate, forming openings in the sacrificial layer, forming color filter elements in the openings, and removing remaining portions of the sacrificial layer that are formed between the color filter elements. | 11-07-2013 |
20140055654 | BACKSIDE ILLUMINATED IMAGE SENSORS WITH STACKED DIES - An image sensor unit may have a backside-illuminated imager and an image co-processor stacked together. The image co-processor may be mounted in a cavity in a permanent carrier. The permanent carrier may include fluid channels that allow cooling fluid to flow past the image co-process and past the imager, thereby removing excess heat generated by the image sensor unit during operation. | 02-27-2014 |
20140084407 | IMAGING SYSTEMS WITH CIRCUIT ELEMENT IN CARRIER WAFER - An imaging system may include an image sensor package with an image sensor wafer mounted on a carrier wafer, which may be a silicon substrate. A capacitor may be formed in the carrier wafer. Trenches may be etched in a serpentine pattern in the silicon substrate. Conductive plates of the capacitor may be formed at least partially in the trenches. An insulator material may be formed between the capacitor and the silicon substrate. A dielectric layer may be formed between the conductive plates of the capacitor. The image sensor package may be mounted on a printed circuit board via a ball grid array. Conductive vias may electrically couple the capacitor and the image sensor wafer to the printed circuit board. | 03-27-2014 |
20140197511 | METHODS FOR FORMING BACKSIDE ILLUMINATED IMAGE SENSORS WITH FRONT SIDE METAL REDISTRIBUTION LAYERS - Methods for forming backside illuminated (BSI) image sensors having metal redistribution layers (RDL) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a BSI image sensor with RDL and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the BSI image sensor. In another embodiment, a BSI image sensor with RDL and solder bumps may be formed using a permanent carrier during manufacture that partially remains in the completed BSI image sensor. A BSI image sensor may be formed before formation of a redistribution layer on the front side of the BSI image sensor. A redistribution layer may, alternatively, be formed on the front side of an image wafer before formation of BSI components such as microlenses and color filters on the back side of the image wafer. | 07-17-2014 |
20150054962 | IMAGING SYSTEMS WITH STACKED IMAGE SENSORS - An imaging system may include a first image sensor die stacked on top of a second image sensor die. A pixel array may include first pixels having photodiodes in the first image sensor die and second pixels having photodiodes in the second image sensor die. The first pixels may be optimized to detect a first type of electromagnetic radiation (e.g., visible light), whereas the second pixels may be optimized to detect a second type of electromagnetic radiation (e.g., infrared light). Light guide channels may be formed in the first image sensor die to help guide incident light to the photodiodes in the second image sensor substrate. The first and second image sensor dies may be bonded at a wafer level. A first image sensor wafer may be a backside illumination image sensor wafer and a second image sensor wafer may be a front or backside illumination image sensor wafer. | 02-26-2015 |
20150054993 | ARRAY CAMERAS WITH LIGHT BARRIERS - An imaging system such as an array camera may include an array of image sensors. The image sensors may each include an array of image pixels formed in a common image sensor substrate. A protective glass cover layer may be provided over the array of image sensors. The cover layer may be attached to the image sensor substrate using an adhesive. The adhesive may be formed on the image sensor substrate in a grid-like pattern in between adjacent image sensors in the array. A light blocking material may be formed on the adhesive grid to minimize optical crosstalk between neighboring image sensors. The light blocking material may fill or partially fill a trench in the adhesive, may coat the outer surfaces of the adhesive, and/or may coat the inner surfaces of the adhesive. If desired, light barriers may also be formed in openings in the glass cover layer. | 02-26-2015 |
20150062420 | IMAGE SENSORS WITH INTERCONNECTS IN COVER LAYER - An image sensor die may include a pixel array formed in an image sensor substrate and covered by a transparent cover layer. The transparent cover layer may be attached to the image sensor substrate using adhesive. Electrical interconnect structures such as conductive vias may be formed in the transparent cover layer and may be used in conveying electrical signals between the image sensor and a printed circuit board. The conductive vias may have one end coupled to a bond pad on the upper surface of the transparent cover layer and an opposing end coupled to a bond pad on the upper surface of the image sensor substrate. The conductive vias may pass through openings that extend through the transparent cover layer and the adhesive. Conductive structures such as wire bonds, stud bumps, or solder balls may be coupled to the bond pads on the surface of the transparent cover layer. | 03-05-2015 |