Patent application number | Description | Published |
20090059648 | FERROELECTRIC SEMICONDUCTOR STORAGE DEVICE - This ferroelectric semiconductor storage device includes: a ferroelectric capacitor; and a transistor having one end of its current path connected to one electrode of the ferroelectric capacitor. A plate line is connected to the other electrode of the ferroelectric capacitor. A word line is connected to the gate of the transistor. A bit line is connected to the other electrode of a capacitor and the other end of the transistor, the capacitor having its one electrode connected to the ground. A bit line potential detection circuit detects a potential of the bit line. A connection circuit provides the same potential between a potential of the plate line and a potential of the bit line based on an output from the bit line potential detection circuit. | 03-05-2009 |
20090219748 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory includes ferroelectric capacitors including ferroelectric films between first electrodes and second electrodes; cell transistors; and a bit line contact connecting the cell transistors to a bit line, wherein the first electrode is connected to one of source and drain of the cell transistor at a first node, so that the ferroelectric capacitor and the cell transistor form a unit cell, the other of source and drain of the cell transistor for the unit cell is connected to the first node of other unit cell to serially connect the cell transistors for unit cells, so that the unit cells form a cell string, the word lines are connected to gates of the cell transistors or function as gates, the plate lines are connected to the second electrodes of the ferroelectric capacitors, and the bit line is connected to a cell transistor at an end of the cell string. | 09-03-2009 |
20100020588 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes cell blocks configured to have a plurality of memory cells connected in series, each memory cell comprising a ferroelectric capacitor and a cell transistor connected in parallel with each other; word lines connected to gates of a plurality of the cell transistors; block selectors connected to first ends of the cell blocks; bit lines connected to the first ends of the cell blocks via the block selectors; and plate lines connected to second ends of the cell blocks, wherein the first ends of first and second cell blocks of the cell blocks respectively sharing the word lines are connected to the same bit line via the block selectors different from each other, and the second ends of the first and the second cell blocks respectively are connected to the plate lines different from each other. | 01-28-2010 |
20100073986 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of cell blocks each of which is configured by serially connecting a plurality of memory cells each of which comprises a ferroelectric capacitor and a cell transistor connected in parallel; a plurality of word lines connected to gates of the cell transistors; a plurality of block selectors each of which comprises an enhancement transistor and a depletion transistor serially connected to each other; a plurality of bit lines connected via the block selectors to one ends of the cell blocks; and a plurality of plate lines connected to the other ends of the cell blocks, wherein a gate length of the enhancement transistor is longer than that of the depletion transistor. | 03-25-2010 |
20110018043 | SEMICONDUCTOR MEMORY DEVICE - A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an area which is between two adjacent ferroelectric capacitors, the second contact plug; first interconnections connected to the second contact plugs, the first interconnections extending in a first direction substantially perpendicular to an arrangement direction, in which the two ferroelectric capacitors are arranged, on the first interlayer film; a second interlayer film above the first interlayer film and the first interconnection; third contact plugs in the second interlayer film, the third contact plugs being respectively connected to the first interconnections at positions shifted from the second contact plugs in the first direction; and second interconnections electrically connecting the third contact plug to the upper electrodes of the two ferroelectric capacitors. | 01-27-2011 |
20110266600 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element. | 11-03-2011 |
20120153414 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes: a plurality of magnetic tunnel junction elements arranged on a semiconductor substrate; and a plurality of selection transistors electrically connected to first ends of the plurality of magnetic tunnel junction elements. A plurality of first bit lines are respectively connected to the first ends of the magnetic tunnel junction elements via one or more of the selection transistors. A plurality of upper electrodes are respectively connected to second ends of the plurality of magnetic tunnel junction elements. A plurality of second bit lines are respectively connected to the second ends of the magnetic tunnel junction elements via the upper electrodes. The upper electrodes extend along the second bit lines, and one of the upper electrodes is commonly connected to the second ends of the plurality of magnetic tunnel junction elements arranged in an extending direction of the second bit lines. | 06-21-2012 |
20120243303 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a magnetic tunnel junction element capable of storing data according to a change in resistance state and rewriting the data using a current. A cell transistor is provided for the magnetic tunnel junction element and is placed in a conducting state when a current is allowed to flow through the magnetic tunnel junction element. A current limiter limits a current flowing through the cell transistor and the magnetic tunnel junction element upon data writing. | 09-27-2012 |
20120314469 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a semiconductor substrate and an active area on the semiconductor substrate. A plurality of cell transistors are formed on the active area. A first bit line and a second bit line are paired with each other. A plurality of word lines intersect the first and second bit lines. A plurality of storage elements respectively has a first end electrically connected to a source or a drain of one of the cell transistors and a second end connected to the first or second bit line. Both of the first and second bit lines are connected to the same active area via the storage elements. | 12-13-2012 |
20120314494 | SEMICONDUCTOR STORAGE DEVICE - In a memory, the MTJ elements respectively have a first end electrically connected to any one of a source and a drain of one of the cell transistors. First bit lines each of which is electrically connected to the other one of the source and the drain of one of the cell transistors. Second bit lines each of which is electrically connected to a second end of one of the MTJ elements. Word lines each of which is electrically connected to a gate of one of the cell transistors or functions as a gate of one of the cell transistors. A plurality of the second bit lines correspond to one of the first bit lines. A plurality of the MTJ elements share the same word line and the same active area. The active area is continuously formed in an extending direction of the first and second bit lines. | 12-13-2012 |