Patent application number | Description | Published |
20080309420 | FRACTIONAL DIVIDER - A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate. | 12-18-2008 |
20100259333 | FRACTIONAL DIVIDER - A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate. | 10-14-2010 |
20120043999 | MEMS STABILIZED OSCILLATOR - A voltage controlled crystal oscillator (VCXO) is locked to a MEMS oscillator with a variable frequency ratio that is a function of a sensed temperature. That allows the long-term stability of the MEMS oscillator and temperature compensation to be reflected in a VCXO output signal having good short-term stability. | 02-23-2012 |
20120105160 | VOLTAGE CONTROLLED OSCILLATOR WITH DITHER - A voltage control signal at a voltage control signal input terminal is used to adjust an output frequency of an oscillator circuit. The voltage level of the voltage control signal is converted in a one-bit analog-to-digital converter (ADC) to a digital output indicative of the voltage level. Successive digital representations of the voltage level of the voltage control signal are upsampled to generate upsampled blocks of data. A dither circuit inserts a digital dither in the upsampled blocks of data to generate dithered upsampled data, which is used to generate a control signal for a feedback divider of a phase-locked loop circuit and thereby adjust the output frequency. | 05-03-2012 |
20120169387 | OSCILLATOR WITH EXTERNAL VOLTAGE CONTROL AND INTERPOLATIVE DIVIDER IN THE OUTPUT PATH - An oscillator output is controlled from an external voltage control terminal using an interpolative divider as a frequency modulator. The oscillator includes a reference clock generator, analog to digital converter, and an interpolative divider. Nominal output frequency is determined by the frequency of the reference clock and the nominal divide value of the interpolative divider. The divide value is changed according to the voltage control input value which is converted to a digital value via an analog to digital converter. Multiple interpolative dividers may be coupled to the single reference clock generator and each have a voltage control input and analog to digital converter. | 07-05-2012 |
20130076415 | PLL USING INTERPOLATIVE DIVIDER AS DIGITALLY CONTROLLED OSCILLATOR - One or more PLLs are formed on an integrated circuit. Each PLL includes an interpolative divider configured as a digitally controlled oscillator, which receives a reference clock signal and supplies an output signal divided according to a divide ratio. A feedback divider is coupled to the output signal of the interpolative divider and supplies a divided output signal as a feedback signal. A phase detector receives the feedback signal and a clock signal to which the PLL locks. The phase detector supplies a phase error corresponding to a difference between the clock signal and the feedback signal and the divide ratio is adjusted according to the phase error. | 03-28-2013 |
20130082793 | Mutual Inductance Circuits - An apparatus includes a first conductive loop coupled to conduct a first current and a second conductive loop coupled in parallel with the first conductive loop and further coupled to conduct a second current. A first conductive portion forms a part of the first conductive loop and the second conductive loop. The first conductive portion is coupled to conduct the first current and the second current. In at least one embodiment of the apparatus, the first conductive loop and the second conductive loop are planar inductors formed in a conductive layer on a substrate of an integrated circuit. | 04-04-2013 |
20140055179 | INTERPOLATIVE DIVIDER LINEARITY ENHANCEMENT TECHNIQUES - A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal. | 02-27-2014 |