Patent application number | Description | Published |
20100169884 | INJECTING TRANSACTIONS TO SUPPORT THE VIRTUALIZATION OF A PHYSICAL DEVICE CONTROLLER - Embodiments of apparatuses, methods, and systems for injecting transactions to support the virtualization of a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, system memory, a physical device controller, and a virtualization agent. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization agent is coupled to the system memory through a first interface and coupled to the physical device controller through a second interface, to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines, and to inject transactions onto the first interface and the second interface on behalf of the plurality of virtual device controllers. | 07-01-2010 |
20100169885 | Paging instruction for a virtualization engine to local storage - Embodiments of apparatuses, methods, and systems for paging instructions for a virtualization engine to local storage are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, a virtualization engine, system memory, and local storage. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization engine is to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines. The local storage is separate from the physical memory to store instructions transferred from the system memory for execution by the virtualization engine. | 07-01-2010 |
20100174841 | PROVIDING MULTIPLE VIRTUAL DEVICE CONTROLLERS BY REDIRECTING AN INTERRUPT FROM A PHYSICAL DEVICE CONTROLLER - Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers. | 07-08-2010 |
20110153914 | REPURPOSING NAND READY/BUSY PIN AS COMPLETION INTERRUPT - A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed. | 06-23-2011 |
20110274414 | BOUNDARY DETECTION IN MEDIA STREAMS - Encoded data decoding techniques. A data decoding agent determines a data segment size for a packet that includes a header and a data segment. The data decoding agent determines a segment end location based, at least in part, on the data segment size. The data decoding agent processes subblocks of data from the data segment. The data decoding agent compares a current location to the segment end location to determine if a current subblock of data from the data segments contains the segment end location. The data decoding agent triggers an exception handler if the current subblock contains the segment end location. | 11-10-2011 |
20110299680 | Methods and Apparatuses for Securing Playback Content - An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine. | 12-08-2011 |
20110320645 | METHOD, APPARATUS AND SYSTEM FOR REDUCED CHANNEL STARVATION IN A DMA ENGINE - Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel. | 12-29-2011 |
20110320777 | DIRECT MEMORY ACCESS ENGINE PHYSICAL MEMORY DESCRIPTORS FOR MULTI-MEDIA DEMULTIPLEXING OPERATIONS - The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction. | 12-29-2011 |
20120155633 | AUDIO CONTENT PROTECTION - In some embodiments an embedded processor is to participate in cryptographic key exchange with an audio software application, and a key exchange communication path is coupled between the audio software application and the embedded processor. Other embodiments are described and claimed. | 06-21-2012 |
20120159128 | Handling Media Streams In A Programmable Bit Processor - In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed. | 06-21-2012 |
20140019676 | REPURPOSING NAND READY/BUSY PIN AS COMPLETION INTERRUPT - A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed. | 01-16-2014 |