Patent application number | Description | Published |
20080217747 | INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES - Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material. | 09-11-2008 |
20080236745 | METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS - A method and apparatus for fabricating or altering a microstructure use means for heating to facilitate a local chemical reaction that forms or alters the submicrostructure. | 10-02-2008 |
20080258198 | STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS - The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising:
| 10-23-2008 |
20080308831 | SEMICONDUCTOR STRUCTURE INCLUDING MIXED RARE EARTH OXIDE FORMED ON SILICON - A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon. | 12-18-2008 |
20080311745 | High Temperature Processing Compatible Metal Gate Electrode For pFETS and Methods For Fabrication - A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO | 12-18-2008 |
20090008725 | METHOD FOR DEPOSITION OF AN ULTRA-THIN ELECTROPOSITIVE METAL-CONTAINING CAP LAYER - A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer. | 01-08-2009 |
20090011610 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE TRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS - A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlO | 01-08-2009 |
20090084435 | Techniques for Cooling Solar Concentrator Devices - Solar concentrator devices and techniques for the fabrication thereof are provided. In one aspect, a solar concentrator device is provided. The solar concentrator device comprises at least one solar converter cell; a heat sink; and a liquid metal between the solar converter cell and the heat sink, configured to thermally couple the solar converter cell and the heat sink during operation of the device. The solar converter cell can comprise a triple-junction semiconductor solar converter cell fabricated on a germanium (Ge) substrate. The heat sink can comprise a vapor chamber heat sink. The liquid metal can comprise a gallium (Ga) alloy and have a thermal resistance of less than or equal to about five square millimeter degree Celsius per Watt (mm | 04-02-2009 |
20090124057 | DAMASCENE GATE FIELD EFFECT TRANSISTOR WITH AN INTERNAL SPACER STRUCTURE - A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel. One method of forming the MOSFET comprises forming the dielectric layer, the gate spacer structure and the gate contact inside a cavity that has been formed by removing a sacrificial gate and spacer structure. | 05-14-2009 |
20090152642 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS - The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric. | 06-18-2009 |
20090217971 | Photovoltaic Devices with Enhanced Efficiencies Using High-Aspect-Ratio Nanostructures - Photovoltaic devices and techniques for enhancing efficiency thereof are provided. In one aspect, a photovoltaic device is provided. The photovoltaic device comprises a photocell having a first photoactive layer and a second photoactive layer adjacent to the first photoactive layer so as to form a heterojunction between the first photoactive layer and the second photoactive layer; and a plurality of high-aspect-ratio nanostructures on one or more surfaces of the second photoactive layer. The plurality of high-aspect-ratio nanostructures are configured to act as a scattering media for incident light. The plurality of high-aspect-ratio nanostructures can also be configured to create an optical resonance effect in the incident light. | 09-03-2009 |
20090217972 | Techniques for Enhancing Efficiency of Photovoltaic Devices Using High-Aspect-Ratio Nanostructures - Photovoltaic devices and techniques for enhancing efficiency thereof are provided. In one aspect, a photovoltaic device is provided. The photovoltaic device comprises a photocell having a photoactive layer and a non-photoactive layer adjacent to the photoactive layer so as to form a heterojunction between the photoactive layer and the non-photoactive layer; and a plurality of high-aspect-ratio nanostructures on one or more surfaces of the photoactive layer. The plurality of high-aspect-ratio nanostructures are configured to act as a scattering media for incident light. The plurality of high-aspect-ratio nanostructures can also be configured to create an optical resonance effect in the incident light. | 09-03-2009 |
20090294876 | METHOD FOR DEPOSITION OF AN ULTRA-THIN ELECTROPOSITIVE METAL-CONTAINING CAP LAYER - A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer. | 12-03-2009 |
20090302369 | METHOD AND APPARATUS FOR FLATBAND VOLTAGE TUNING OF HIGH-K FIELD EFFECT TRANSISTORS - In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor. | 12-10-2009 |
20090302370 | METHOD AND APPARATUS FOR FLATBAND VOLTAGE TUNING OF HIGH-K FIELD EFFECT TRANSISTORS - In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor. | 12-10-2009 |
20100044678 | METHOD OF PLACING A SEMICONDUCTING NANOSTRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTING NANOSTRUCTURE - A method of placing a functionalized semiconducting nanostructure, includes functionalizing a semiconducting nanostructure including one of a nanowire and a nanocrystal, with an organic functionality including a functional group for bonding to a bonding surface, dispersing the functionalized semiconducting nanostructure in a solvent to form a dispersion, and depositing the dispersion onto the bonding surface. | 02-25-2010 |
20100065815 | SEMICONDUCTOR STRUCTURE INCLUDING MIXED RARE EARTH OXIDE FORMED ON SILICON - A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon. | 03-18-2010 |
20100103721 | Heater and memory cell, memory device and recording head including the heater - A heater includes at least two leads, and a heating element which is formed between the at least two leads, a material of the heating element being different from a material of the at least two leads such that a location of a hot spot in the heater is controllable based on a polarity of current in the heater. | 04-29-2010 |
20100108131 | Techniques for Use of Nanotechnology in Photovoltaics - Techniques for combining nanotechnology with photovoltaics are provided. In one aspect, a method of forming a photovoltaic device is provided comprising the following steps. A plurality of nanowires are formed on a substrate, wherein the plurality of nanowires attached to the substrate comprises a nanowire forest. In the presence of a first doping agent and a first volatile precursor, a first doped semiconductor layer is conformally deposited over the nanowire forest. In the presence of a second doping agent and a second volatile precursor, a second doped semiconductor layer is conformally deposited over the first doped layer. The first doping agent comprises one of an n-type doping agent and a p-type doping agent and the second doping agent comprises a different one of the n-type doping agent and the p-type doping agent from the first doping agent. A transparent electrode layer is deposited over the second doped semiconductor layer. | 05-06-2010 |
20100218813 | SILICON WAFER BASED STRUCTURE FOR HETEROSTRUCTURE SOLAR CELLS - A multi-junction photovoltaic device includes a silicon substrate and a dielectric layer formed on the silicon substrate. A germanium layer is formed on the dielectric layer. The germanium includes a crystalline structure that is substantially similar to the crystalline structure of the silicon substrate. A first photovoltaic sub-cell includes a first plurality of doped semiconductor layers formed on the germanium layer. At least a second photovoltaic sub-cell includes a second plurality of doped semiconductor layers formed on the first photovoltaic sub-cell that is on the germanium layer that is on the dielectric layer. | 09-02-2010 |
20100327259 | Ultra-Sensitive Detection Techniques - Techniques for ultra-sensitive detection are provided. In one aspect, a detection device is provided. The detection device comprises a source; a drain; a nanowire comprising a semiconductor material having a first end clamped to the source and a second end clamped to the drain and suspended freely therebetween; and a gate in close proximity to the nanowire. | 12-30-2010 |
20100330687 | ULTRA-SENSITIVE DETECTION TECHNIQUES - Techniques for ultra-sensitive detection are provided. In one aspect, a detection device is provided. The detection device comprises a source; a drain; a nanowire comprising a semiconductor material having a first end clamped to the source and a second end clamped to the drain and suspended freely therebetween; and a gate in close proximity to the nanowire. | 12-30-2010 |
20110019525 | HEATER AND MEMORY CELL, MEMORY DEVICE AND RECORDING HEAD INCLUDING THE HEATER - A memory cell includes at least one heater, and at least two leads and a heating element which is formed between at least two leads, a material of the heating element being different from a material of at least two leads such that a location of a hot spot in the heater is controllable based on a polarity of current in the heater and at least one storage medium formed adjacent to at least one heater. | 01-27-2011 |
20110156133 | SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME - A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm. | 06-30-2011 |
20110165724 | TECHNIQUES FOR USE OF NANOTECHNOLOGY IN PHOTOVOLTAICS - Techniques for combining nanotechnology with photovoltaics are provided. In one aspect, a method of forming a photovoltaic device is provided comprising the following steps. A plurality of nanowires are formed on a substrate, wherein the plurality of nanowires attached to the substrate comprises a nanowire forest. In the presence of a first doping agent and a first volatile precursor, a first doped semiconductor layer is conformally deposited over the nanowire forest. In the presence of a second doping agent and a second volatile precursor, a second doped semiconductor layer is conformally deposited over the first doped layer. The first doping agent comprises one of an n-type doping agent and a p-type doping agent and the second doping agent comprises a different one of the n-type doping agent and the p-type doping agent from the first doping agent. A transparent electrode layer is deposited over the second doped semiconductor layer. | 07-07-2011 |
20110165767 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS - The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric. | 07-07-2011 |
20110168247 | Techniques for Cooling Solar Concentrator Devices - Solar concentrator devices and techniques for the fabrication thereof are provided. In one aspect, a solar concentrator device is provided. The solar concentrator device comprises at least one solar converter cell; a heat sink; and a liquid metal between the solar converter cell and the heat sink, configured to thermally couple the solar converter cell and the heat sink during operation of the device. The solar converter cell can comprise a triple junction semiconductor solar converter cell fabricated on a germanium (Ge) substrate. The heat sink can comprise a vapor chamber heat sink. The liquid metal can comprise a gallium (Ga) alloy and have a thermal resistance of less than or equal to about five square millimeter degree Celsius per Watt (mm | 07-14-2011 |
20110180777 | METHOD OF PLACING A SEMICONDUCTING NANOSTRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTING NANOSTRUCTURE - A semiconductor device includes a bonding surface, a semiconducting nanostructure including one of a nanowire and a nanocrystal, which is formed on the bonding surface, and a source electrode and a drain electrode which are formed on the nanostructure such that the nanostructure is electrically connected to the source and drain electrodes. | 07-28-2011 |
20110201163 | SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME - A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm. | 08-18-2011 |
20110235390 | HIGH DENSITY MEMORY DEVICE - A memory device and a method of forming the same are provided. The memory device includes a substrate; a set of electrodes disposed on the substrate; a dielectric layer formed between the set of electrodes; and a transition metal oxide layer formed between the set of electrodes, the transition metal oxide layer configured to undergo a metal-insulator transition (MIT) to perform a read or write operation. | 09-29-2011 |
20110284073 | HOLEY ELECTRODE GRIDS FOR PHOTOVOLTAIC CELLS WITH SUBWAVELENGTH AND SUPERWAVELENGTH FEATURE SIZES - A photovoltaic cell and a method of forming an electrode grid on a photovoltaic semiconductor substrate of a photovoltaic cell are disclosed. In one embodiment, the photovoltaic cell comprises a photovoltaic semiconductor substrate; a back electrode electrically connected to a back surface of the substrate; and a front electrode electrically connected to a front surface of the substrate. The substrate, back electrode, and front electrode form an electric circuit for generating an electric current when said substrate absorbs light. The front electrode is comprised of a metal grid defining a multitude of holes. These holes may be periodic, aperiodic, or partially periodic. The front electrode may be formed by depositing nanospheres on the substrate; forming a metallic layer on the substrate, around the nanospheres; and removing the nanospheres, leaving an electrode grid defining a multitude of holes on the substrate. | 11-24-2011 |
20120070936 | ANNEALING THIN FILMS - In an annealing process, a Kesterite film is provided on a substrate. The Kesterite film and the substrate are generally planar, have an interface, and have a substrate exterior side and a Kesterite exterior side. An additional step includes locating the cap adjacent the Kesterite exterior side. A further step includes applying sufficient heat to the Kesterite film and the substrate for a sufficient time to anneal the Kesterite film. The annealing is carried out with the cap adjacent the Kesterite exterior side. In another aspect, the film is not limited to Kesterite, and the cap is employed without any precursor layer thereon. Solar cell manufacturing techniques employing the annealing techniques are also disclosed. | 03-22-2012 |
20120097234 | Using Diffusion Barrier Layer for CuZnSn(S,Se) Thin Film Solar Cell - Techniques for fabricating thin film solar cells, such as CuZnSn(S,Se) (CZTSSe) solar cells are provided. In one aspect, a method of fabricating a solar cell is provided that includes the following steps. A substrate is provided. The substrate is coated with a molybdenum (Mo) layer. A stress-relief layer is deposited on the Mo layer. The stress-relief layer is coated with a diffusion barrier. Absorber layer constituent components are deposited on the diffusion barrier, wherein the constituent components comprise one or more of sulfur (S) and selenium (Se). The constituent components are annealed to form an absorber layer, wherein the stress-relief layer relieves thermal stress imposed on the absorber layer, and wherein the diffusion barrier blocks diffusion of the one or more of S and Se into the Mo layer. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer. | 04-26-2012 |
20120100663 | Fabrication of CuZnSn(S,Se) Thin Film Solar Cell with Valve Controlled S and Se - Techniques for fabricating thin film solar cells are provided. In one aspect, a method of fabricating a solar cell includes the following steps. A molybdenum (Mo)-coated substrate is provided. Absorber layer constituent components, two of which are sulfur (S) and selenium (Se), are deposited on the Mo-coated substrate. The S and Se are deposited on the Mo-coated substrate using thermal evaporation in a vapor chamber. Controlled amounts of the S and Se are introduced into the vapor chamber to regulate a ratio of the S and Se provided for deposition. The constituent components are annealed to form an absorber layer on the Mo-coated substrate. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer. | 04-26-2012 |
20120100664 | FABRICATING KESTERITE SOLAR CELLS AND PARTS THEREOF - A Kesterite film is vacuum deposited and annealed on a substrate. Deposition is conducted at low temperature to provide good composition control and efficient use of metals. Annealing is conducted at a high temperature for a short period of time. Thermal evaporation, E-beam evaporation or sputtering in a high vacuum environment may be employed as part of a deposition process. | 04-26-2012 |
20120125433 | GRID-LINE-FREE CONTACT FOR A PHOTOVOLTAIC CELL - Electrical contact to the front side of a photovoltaic cell is provided by an array of conductive through-substrate vias, and optionally, an array of conductive blocks located on the front side of the photovoltaic cell. A dielectric liner provides electrical isolation of each conductive through-substrate via from the semiconductor material of the photovoltaic cell. A dielectric layer on the backside of the photovoltaic cell is patterned to cover a contiguous region including all of the conductive through-substrate vias, while exposing a portion of the backside of the photovoltaic cell. A conductive material layer is deposited on the back surface of the photovoltaic cell, and is patterned to form a first conductive wiring structure that electrically connects the conductive through-substrate vias and a second conductive wiring structure that provides electrical connection to the backside of the photovoltaic cell. | 05-24-2012 |
20120138132 | SILICON WAFER BASED STRUCTURE FOR HETEROSTRUCTURE SOLAR CELLS - A multi-junction photovoltaic device includes a silicon substrate and a dielectric layer formed on the silicon substrate. A germanium layer is formed on the dielectric layer. The germanium includes a crystalline structure that is substantially similar to the crystalline structure of the silicon substrate. A first photovoltaic sub-cell includes a first plurality of doped semiconductor layers formed on the germanium layer. At least a second photovoltaic sub-cell includes a second plurality of doped semiconductor layers formed on the first photovoltaic sub-cell that is on the germanium layer that is on the dielectric layer. | 06-07-2012 |
20120186626 | SOLAR ENERGY COLLECTION SYSTEM - A solar energy collection system includes a reference member, a support member rotatably mounted relative to the reference member, and a drive system operatively coupled between the reference member and the support member. The drive system includes a linear actuator having a fixed portion operatively connected to the reference member and a strut portion that is selectivity extendable relative to the fixed portion. The strut portion includes an end section. A first connector member is operatively connected between the reference member and the end section of the strut portion, and a second connector member is operatively connected between the support member and the end section of the strut portion. Selective extension and retraction of the strut portion relative to the fixed portion selectively shifts the support member along a desired path. | 07-26-2012 |
20120196401 | Nano/Microwire Solar Cell Fabricated by Nano/Microsphere Lithography - Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof. The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof. A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires. | 08-02-2012 |
20120201956 | METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS - A method and apparatus for fabricating or altering a microstructure use means for heating to facilitate a local chemical reaction that forms or alters the submicrostructure. | 08-09-2012 |
20120270385 | SWITCHING DEVICE HAVING A MOLYBDENUM OXYNITRIDE METAL GATE - A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate. | 10-25-2012 |
20120300534 | HIGH DENSITY MEMORY DEVICE - A method of operating a memory device having a dielectric material layer, a transition metal oxide layer and a set of electrodes each formed over a substrate, includes applying a voltage across the set of electrodes producing an electric field across the transition metal oxide layer enabling the transition metal oxide layer to undergo a metal-insulation transition (MIT) to perform a read or write operation on memory device. | 11-29-2012 |
20130013206 | Meteorological Parameter Forecasting - A method, an apparatus and an article of manufacture for forecasting a meteorological parameter. The method includes analyzing geographically distributed sensor network data to assess spatial and temporal variation of a meteorological parameter in real-time, correlating at least two portions of data from the sensor network to identify a temporal and spatial evolution of the meteorological parameter, and forecasting the meteorological parameter based on the temporal and spatial evolution of the meteorological parameter. | 01-10-2013 |
20130035860 | Meteorological Parameter Forecasting - A method, an apparatus and an article of manufacture for forecasting a meteorological parameter. The method includes analyzing geographically distributed sensor network data to assess spatial and temporal variation of a meteorological parameter in real-time, correlating at least two portions of data from the sensor network to identify a temporal and spatial evolution of the meteorological parameter, and forecasting the meteorological parameter based on the temporal and spatial evolution of the meteorological parameter. | 02-07-2013 |
20130199594 | TRANSPORTABLE PHOTOVOLTAIC SYSTEM - A transportable photovoltaic system includes a plurality of photovoltaic devices, a composite frame to which the plurality of photovoltaic devices are affixed, and a base structure to which the composite frame is movably attached through at least one variable-angle mount structure. The orientation of the frame and the light concentrating elements relative to the base structure can be altered employing the at least one variable-angle mount structure. The frame and the plurality of photovoltaic devices can be assembled prior to shipping, and the base structure can be manufactured on site. The transportable photovoltaic system is not affixed to ground or other fixture, but can be picked up at any time during the operational lifetime. The transportable photovoltaic system can be rapidly deployed with little or no site preparation requirement other than generally level ground, and can be retracted to a lower exposure position to avoid storm and/or hazardous conditions. | 08-08-2013 |
20130199597 | TRANSPORTABLE PHOTOVOLTAIC SYSTEM - A transportable photovoltaic system includes a plurality of photovoltaic devices, a composite frame to which the plurality of photovoltaic devices are affixed, and a base structure to which the composite frame is movably attached through at least one variable-angle mount structure. The orientation of the frame and the light concentrating elements relative to the base structure can be altered employing the at least one variable-angle mount structure. The frame and the plurality of photovoltaic devices can be assembled prior to shipping, and the base structure can be manufactured on site. The transportable photovoltaic system is not affixed to ground or other fixture, but can be picked up at any time during the operational lifetime. The transportable photovoltaic system can be rapidly deployed with little or no site preparation requirement other than generally level ground, and can be retracted to a lower exposure position to avoid storm and/or hazardous conditions. | 08-08-2013 |
20140034118 | THIN FILM SOLAR CELLS - Embodiments relate to a solar cell apparatus including a molybdenum (Mo) contact layer and an annealed absorber layer including zinc and sulfur directly adjacent to the Mo contact layer. The apparatus has no molybdenum disulfide (MoS | 02-06-2014 |
20140038344 | THIN FILM SOLAR CELLS - Embodiments relate to a method including forming a layer of copper zinc tin sulfide (CZTS) on a first layer of molybdenum (Mo) and annealing the CZTS layer and the first Mo layer to form a layer of molybdenum disulfide (MoS | 02-06-2014 |
20140041718 | Photovoltaic Devices with Enhanced Efficiencies Using High-Aspect Ratio Nanostructures - Photovoltaic devices and techniques for enhancing efficiency thereof are provided. In one aspect, a photovoltaic device is provided. The photovoltaic device comprises a photocell having a first photoactive layer and a second photoactive layer adjacent to the first photoactive layer so as to form a heterojunction between the first photoactive layer and the second photoactive layer; and a plurality of high-aspect-ratio nanostructures on one or more surfaces of the second photoactive layer. The plurality of high-aspect-ratio nanostructures are configured to act as a scattering media for incident light. The plurality of high-aspect-ratio nanostructures can also be configured to create an optical resonance effect in the incident light. | 02-13-2014 |
20140069490 | Lead Frame Package for Solar Concentrators - Techniques for providing high-capacity, re-workable connections in concentrated photovoltaic devices are provided. In one aspect, a lead frame package for a photovoltaic device is provided that includes a beam shield; and one or more lead frame connectors affixed to the beam shield, wherein the lead frame connectors are configured to provide connection to the photovoltaic device when the photovoltaic device is assembled to the lead frame package. A photovoltaic apparatus is also provided that includes a lead frame package assembled to a photovoltaic device. The lead frame package includes a beam shield and one or more lead frame connectors affixed to the beam shield, wherein the lead frame connectors are configured to provide connection to the photovoltaic device. | 03-13-2014 |
20140069491 | Interposer Connector for High Power Solar Concentrators - In one aspect, an interposer assembly for housing a photovoltaic device includes a frame, formed from an electrically insulating material, having a center opening with a shape/size complementary to a shape/size of the photovoltaic device thus permitting the photovoltaic device to fit within the center opening in the frame when the photovoltaic device is housed in the assembly; a beam shield on the frame having a cup-shaped inner cavity to aid in routing of light to the photovoltaic device, wherein a side of the beam shield facing the frame has one or more recesses present therein; and one or more interposer connectors positioned between the frame and the beam shield such that the interposer connectors fit within the recesses in the beam shield, and wherein a portion of each of the interposer connectors extends into the center opening of the frame. | 03-13-2014 |
20140127870 | SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME - A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm. | 05-08-2014 |
20140127888 | SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME - A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm. | 05-08-2014 |
20140166752 | METHOD AND APPARATUS TO TAG METAL - A method of tagging an article is disclosed. Data that identifies the article is encoded into at least one stress value. A stress region having a stress that corresponds to the at least one stress value is created in a surface of the article to the tag the article. The at least one stress value is read by a measurement device to read the data and identify the article. | 06-19-2014 |
20140166753 | METHOD AND APPARATUS TO TAG METAL - A method of tagging an article is disclosed. Data that identifies the article is encoded into at least one stress value. A stress region having a stress that corresponds to the at least one stress value is created in a surface of the article to the tag the article. The at least one stress value is read by a measurement device to read the data and identify the article. | 06-19-2014 |
20140305499 | PROTECTIVE INSULATING LAYER AND CHEMICAL MECHANICAL POLISHING FOR POLYCRYSTALLINE THIN FILM SOLAR CELLS - A method for forming a photovoltaic device includes forming an absorber layer with a granular structure on a conductive layer; conformally depositing an insulating protection layer over the absorber layer to fill in between grains of the absorber layer; and planarizing the protection layer and the absorber layer. A buffer layer is formed on the absorber layer, and a top transparent conductor layer is deposited over the buffer layer. | 10-16-2014 |
20140306306 | PROTECTIVE INSULATING LAYER AND CHEMICAL MECHANICAL POLISHING FOR POLYCRYSTALLINE THIN FILM SOLAR CELLS - A method for forming a photovoltaic device includes forming an absorber layer with a granular structure on a conductive layer; conformally depositing an insulating protection layer over the absorber layer to fill in between grains of the absorber layer; and planarizing the protection layer and the absorber layer. A buffer layer is formed on the absorber layer, and a top transparent conductor layer is deposited over the buffer layer. | 10-16-2014 |