Patent application number | Description | Published |
20100047957 | METHOD FOR FORMING SOLAR CELL HAVING ACTIVE REGION WITH NANOSTRUCTURES HAVING ENERGY WELLS - A method and apparatus for solar cell having graded energy wells is provided. The active region of the solar cell comprises nanostructures. The nanostructures are formed from a material that comprises a III-V compound semiconductor and an element that alters the band gap of the III-V compound semiconductor. For example, the III-V compound semiconductor could be gallium nitride (GaN). As an example, the “band gap altering element” could be indium (In). The concentration of the indium in the active region is non-uniform such that the active region has a number of energy wells, separated by barriers. The energy wells may be “graded”, by which it is meant that the energy wells have a different band gap from one another, generally increasing or decreasing from one well to another monotonically. | 02-25-2010 |
20100236617 | Stacked Structure Solar Cell Having Backside Conductive Contacts - A solar cell having back side conductive contacts and method for forming the solar cell is provided. One embodiment is a solar cell having back side conductive contacts. The solar cell has a first region of a first material having a first conductivity over a front side of a substrate, a second region of a second material conformably on the first material, and a third region of a third material having a second conductivity conformably on the second material. The first region, the second region, and the third region form a structure that generates charge carriers from solar radiation. The solar cell has a first conductive contact and a second conductive contact exposed on the back side of the substrate. The first conductive contact is in electrical contact with the first material and the second conductive contact is in electrical contact with the third material. | 09-23-2010 |
20100264454 | SEMICONDUCTOR LIGHT EMITTING DEVICE GROWING ACTIVE LAYER ON TEXTURED SURFACE - In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface. | 10-21-2010 |
20100327256 | CONTROLLING PIT FORMATION IN A III-NITRIDE DEVICE - A device includes a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region and a plurality of layer pairs disposed within one of the n-type region and the p-type region. Each layer pair includes an InGaN layer and pit-filling layer in direct contact with the InGaN layer. The pit-filling layer may fill in pits formed in the InGaN layer. | 12-30-2010 |
20110177631 | METHOD OF FORMING A COMPOSITE SUBSTRATE AND GROWING A III-V LIGHT EMITTING DEVICE OVER THE COMPOSITE SUBSTRATE - A method according to embodiments of the invention includes providing a substrate comprising a host and a seed layer bonded to the host. The seed layer comprises a plurality of regions. A semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region is grown on the substrate. A top surface of a semiconductor layer grown on the seed layer has a lateral extent greater than each of the plurality of seed layer regions. | 07-21-2011 |
20110297214 | MULTI-JUNCTION SOLAR CELL HAVING SIDEWALL BI-LAYER ELECTRICAL INTERCONNECT - Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may be a multi junction solar cell. The optoelectronic device may have a bi-layer electrical interconnect that is physically and electrically connected to sidewalls of the array of nanostructures. The optoelectronic device may be operated as a multi junction solar cell, wherein each junction is associated with one portion of the device. The bi-layer electrical interconnect allows current to pass from one portion to the next. Thus, the bi-layer electrical interconnect may serve as a replacement for a tunnel junction, which is used in some conventional multi junction solar cells. | 12-08-2011 |
20110297913 | NANOSTRUCTURE OPTOELECTRONIC DEVICE HAVING SIDEWALL ELECTRICAL CONTACT - Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may have a top electrical contact that is physically and electrically connected to sidewalls of the array of nanostructures (e.g., nanocolumns). The top electrical contact may be located such that light can enter or leave the nanostructures without passing through the top electrical contact. Therefore, the top electrical contact can be opaque to light having wavelengths that are absorbed or generated by active regions in the nanostructures. The top electrical contact can be made from a material that is highly conductive, as no tradeoff needs to be made between optical transparency and electrical conductivity. The device could be a solar cell, LED, photo-detector, etc. | 12-08-2011 |
20110299074 | NANOSTRUCTURE OPTOELECTRONIC DEVICE WITH INDEPENDENTLY CONTROLLABLE JUNCTIONS - Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may have one or more intermediate electrical contacts that are physically and electrically connected to sidewalls of the array of nanostructures. The contacts may allow different photo-active regions of the optoelectronic device to be independently controlled. For example, one color light may be emitted or detected independently of another using the same group of one or more nanostructures. The optoelectronic device may be a pixilated device that may serve as an LED display or imaging sensor. The pixilated device may have an array of nanostructures with alternating rows and columns of sidewall electrical contacts at different layers. A pixel may be formed at the intersection of a row contact and a column contact. As one example, a single group of one or more nanostructures has a blue sub-pixel, a green sub-pixel, and a red sub-pixel. | 12-08-2011 |
20120025169 | NANOSTRUCTURE ARRAY TRANSISTOR - Transistors and methods for forming transistors from groups of nanostructures are disclosed herein. The transistor may be formed from an array of nanostructures that are grown vertically on a substrate. The nanostructures may have lower, middle and upper segments that may be formed with different materials and/or doping to achieve desired effects. Collectively, the lower segments may form the source or drain, with the middle segments collectively forming the channel. Alternatively, the lower segments could collectively form the emitter or collector, with the middle segments collectively forming the base. Transistor electrodes may be planar metal structures that surround sidewalls of the nanostructures. The transistors may be Field Effect Transistors (FETs) or bipolar junction transistors (BJTs). Heterojunction bipolar junction transistors (HBTs) and high electron mobility transistors (HEMTs) are possible. | 02-02-2012 |
20120205691 | Controlling Pit Formation in a III-Nitride Device - A device includes a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region and a plurality of layer pairs disposed within one of the n-type region and the p-type region. Each layer pair includes an InGaN layer and pit-filling layer in direct contact with the InGaN layer. The pit-filling layer may fill in pits formed in the InGaN layer. | 08-16-2012 |
20130075693 | COALESCED NANOWIRE STRUCTURES WITH INTERSTITIAL VOIDS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer. | 03-28-2013 |
20140134769 | NANOSTRUCTURE OPTOELECTRONIC DEVICE WITH INDEPENDENTLY CONTROLLABLE JUNCTIONS - Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may have one or more intermediate electrical contacts that are physically and electrically connected to sidewalls of the array of nanostructures. The contacts may allow different photo-active regions of the optoelectronic device to be independently controlled. For example, one color light may be emitted or detected independently of another using the same group of one or more nanostructures. The optoelectronic device may be a pixilated device that may serve as an LED display or imaging sensor. The pixilated device may have an array of nanostructures with alternating rows and columns of sidewall electrical contacts at different layers. A pixel may be formed at the intersection of a row contact and a column contact. As one example, a single group of one or more nanostructures has a blue sub-pixel, a green sub-pixel, and a red sub-pixel. | 05-15-2014 |