Patent application number | Description | Published |
20120113344 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a light generating part and a display panel. The display panel includes a first substrate, and a second substrate facing the first substrate. The second substrate includes a plurality of pixel units including a sensor sensing the light generated from the light generating part and reflected from an object disposed on the display panel, and a pixel. The display panel further includes a light blocking member which is positioned at a position corresponding to an area in which the sensor is disposed and prevents the light generated from the light generating part from being directly incident to the sensor. The light blocking member is disposed on the first substrate. | 05-10-2012 |
20120138960 | LIGHT SENSOR AND DISPLAY APPARATUS HAVING THE SAME - In a display apparatus, a light sensor of a display includes a light sensing layer, a source electrode, a drain electrode, an insulating layer, and a gate electrode to sense light from an external source. The light sensing layer is disposed on the substrate to sense light, and the source and drain electrodes are disposed on the light sensing layer and are covered by the insulating layer. The gate electrode is disposed on the insulating layer. An edge of the gate electrode is disposed on the light sensing layer at least in an area where the light sensing layer is overlapped with the source and drain electrodes. | 06-07-2012 |
20120182277 | DISPLAY PANEL HAVING EMBEDDED LIGHT SENSORS - A display panel includes a plurality of pixels disposed on a first panel substrate of first and second panel substrates that face each other and cooperate to display an image. The second panel substrate includes a base substrate, a read-out line, a first insulating layer, a scan line, a switching device, and a light sensor. The read-out line is disposed on the base substrate and extended in a direction. The first insulating layer is disposed on the read-out line. The scan line is extended to cross the read-out line and disposed on the first insulating layer. The switching device includes a first electrode connected to the scan line, a second electrode connected to a read-out line, and a third electrode spaced apart from the second electrode. The light sensor is structured to selectively detect lights of predetermined wavelengths and connected to the third electrode of the switching device. | 07-19-2012 |
20130033455 | LIGHT SENSING PANEL AND DISPLAY APPARATUS HAVING THE SAME - A light sensing panel includes sensors arranged in rows and columns, where the sensors receive a first bias voltage and a second bias voltage and output light sensing signals based on light incident thereto; first and second bias lines which transfers the first and second bias voltages, respectively, to the sensors, where each of the first and second bias lines includes a main line and sub lines diverged from the main line and arranged in a second direction corresponding to the columns;, where the sub lines of the first and second bias lines are alternately arranged, and where when two adjacent sub lines are shorted, the shorted sub line of the first bias line is separated from the main line of the first bias line. | 02-07-2013 |
20130075763 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING TOUCH SUBSTRATE - A display apparatus includes a first substrate including a plurality of pixels, and a second substrate facing the first substrate, the second substrate comprising a sensor area and a peripheral area, the sensor area comprising a plurality of sensors. The second substrate includes an insulating layer, and a plurality of lines disposed on the insulating layer corresponding to the peripheral area and connected to the sensors. A void is formed in the insulating layer between two adjacent lines of the plurality of lines at a boundary of the sensor area and the peripheral area. | 03-28-2013 |
20130229401 | DISPLAY APPARATUS - A display apparatus includes pixels, a driver for providing a driving voltage, and conductive lines including a first line, a second line, and a third line. The display apparatus further includes a first circuit electrically connected to the driver for receiving the driving voltage and electrically connected to the pixels for controlling the pixels. The first circuit includes a first chip, a first inner line, a first pad, a second pad, a third pad, a fourth pad, and a fifth pad. The first chip is electrically connected to the driver through the third pad, the fourth pad, the fifth pad, the third line, the second line, the second pad, the first inner line, the first pad, and the first line. The fourth and fifth pads may contribute to consistent resistance for paths that transmit the driving voltage, for enabling desirable display quality of the display apparatus. | 09-05-2013 |
Patent application number | Description | Published |
20140048894 | MTP MTJ DEVICE - Systems and methods for multiple-time programmable (MTP) devices. An MTP device includes a magnetic tunnel junction (MTJ) device programmable to a plurality of states based on voltage applied across the MTJ device. The plurality of states include a first resistance state corresponding to a first binary value stored in the MTJ device based on a first voltage, a second resistance state corresponding to a second binary value stored in the MTJ device based on a second voltage, a third resistance state corresponding to a breakdown of a barrier layer of the MTJ device based on a third voltage, and a fourth resistance state corresponding to an open fuse based on a fourth voltage. | 02-20-2014 |
20140063922 | MRAM WORD LINE POWER CONTROL SCHEME - Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated, with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro. | 03-06-2014 |
20140071738 | REFERENCE CELL REPAIR SCHEME - In a magnetic random access memory (MRAM), numerous arrays of reference bit cells are coupled together by coupling their respective bit lines to a merged reference node. Pass gate circuitry coupled between the respective reference bit lines and the merged reference node is configured for selectively coupling or decoupling one or more of the reference bit lines to and from the merged reference node. The pass gate circuitry is controllable by programming one-time programmable devices coupled to the pass gate circuitry. The one-time programmable devices can be programmed to decouple flawed arrays of reference bit cells from the merged reference node or to select between redundant arrays of reference bit cells for coupling to the reference node. | 03-13-2014 |
20140071739 | REFERENCE LEVEL ADJUSTMENT SCHEME - A tunable reference cell scheme for magnetic random access memory (MRAM) circuitry selectively couples reference cells and data cells to shared write driver circuitry. Magnetic tunnel junctions (MTJs) in the reference cells can be programmed to a selected magnetic orientation using the shared write driver circuitry. The programmed reference cells can be merged with other programmed reference cells and/or with fixed reference cells to produce a tunable reference level for comparison with MTJ data cells during a read operation. Sharing write driver circuitry between data cells and reference cells allows programming of reference cells without consuming increased area on a chip or macro. | 03-13-2014 |
20140071740 | OTP SCHEME WITH MULTIPLE MAGNETIC TUNNEL JUNCTION DEVICES IN A CELL - A one time programming (OTP) apparatus unit cell includes multiple magnetic tunnel junctions (MTJs) and a shared access transistor coupled between the multiple MTJs and a fixed potential. Each of the multiple MTJs in a unit cell can be coupled to separate programming circuitry and/or separate sense amplifier circuitry so that they can be individually programmed and/or individually sensed. A logical combination from the separate sense amplifiers can be generated as an output of the unit cell. | 03-13-2014 |
20140140162 | MEMORY CELL ARRAY WITH RESERVED SECTOR FOR STORING CONFIGURATION INFORMATION - A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device. | 05-22-2014 |
20140215294 | ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS - A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element. | 07-31-2014 |
20150022264 | SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION - A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line. | 01-22-2015 |
20150070978 | SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL - An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. Each of the four MTJ cells is coupled to a distinct word line. Each of the four MTJ cells includes an MTJ element and a single transistor. The single transistor of each particular MTJ cell is configured to enable read access to the MTJ element of the particular MTJ cell. | 03-12-2015 |