Patent application number | Description | Published |
20130339583 | SYSTEMS AND METHODS FOR TRANSFERRING DATA OUT OF ORDER IN NEXT GENERATION SOLID STATE DRIVE CONTROLLERS - Systems and methods are provided for transferring data back and forth from a NAND based storage device by issuing instructions for reading an allocation unit. The instructions may be issued out of order with respect to a sequential order of the data. The allocation unit related information is stored in a linked list data structure. The stored linked list data structure may be accessed for processing the allocation unit related information out of order with respect to the sequential order of the data. | 12-19-2013 |
20140108714 | APPARATUS AND METHOD FOR GENERATING DESCRIPTORS TO TRANSFER DATA TO AND FROM NON-VOLATILE SEMICONDUCTOR MEMORY OF A STORAGE DRIVE - A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory. | 04-17-2014 |
20140195727 | APPARATUS AND METHOD FOR GENERATING DESCRIPTORS TO REACCESS A NON-VOLATILE SEMICONDUCTOR MEMORY OF A STORAGE DRIVE DUE TO AN ERROR - A storage drive including a first module and a second module. The first module is configured to, based on an instruction signal of a first descriptor, transfer a block of data to or from a non-volatile semiconductor memory in the storage drive. The second module is configured to: monitor a status of the transfer of the block of data; determine whether an error exists with respect to the transfer of the block of data; and independent of communication with a host device, initiate generation of a second descriptor if the error exists. The second module is configured to, according to the second descriptor, perform a reaccess event including reaccessing the non-volatile semiconductor memory to again transfer the block of data to or from the non-volatile semiconductor memory. | 07-10-2014 |
Patent application number | Description | Published |
20090268043 | LARGE DYNAMIC RANGE CAMERAS - A digital camera includes a plurality of channels and a processing component operatively coupled to the plurality of channels. Each channel of the plurality of channels includes an optics component and a sensor that includes an array of photo-detectors. The processing component is configured to separately control an integration time of each channel, where a first integration time of a first channel is less than a second integration time of a second channel. The processing component is also configured to combine data from the plurality of channels to generate an image. | 10-29-2009 |
20100060746 | Simultaneous multiple field of view digital cameras - Digital camera systems and methods are described that provide digital cameras configured to simultaneously acquire image data via multiple channels having different fields of view. The digital cameras include multiple channels coupled to a processing component. Each channel includes an optics component and an array of sensors or photo-detectors integrated on a semiconductor substrate. The channels include a first channel having a first field of view (FOV) and a second channel having a second FOV, and the second FOV is different than the first FOV. The processing component is configured to independently control simultaneous data acquisition with each of the channels, and to combine data from at least one channel during a frame to provide a high resolution image. | 03-11-2010 |
20100208100 | Digital camera with multiple pipeline signal processors - There are many, many inventions described herein. In one aspect, what is disclosed is a digital camera including a plurality of arrays of photo detectors, including a first array of photo detectors to sample an intensity of light of a first wavelength and a second array of photo detectors to sample an intensity of light of a second wavelength. The digital camera further may also include a first lens disposed in an optical path of the first array of photo detectors, wherein the first lens includes a predetermined optical response to the light of the first wavelength, and a second lens disposed in with an optical path of the second array of photo detectors wherein the second lens includes a predetermined optical response to the light of the second wavelength. In addition, the digital camera may include signal processing circuitry, coupled to the first and second arrays of photo detectors, to generate a composite image using (i) data which is representative of the intensity of light sampled by the first array of photo detectors, and (ii) data which is representative of the intensity of light sampled by the second array of photo detectors; wherein the first array of photo detectors, the second array of photo detectors, and the signal processing circuitry are integrated on or in the same semiconductor substrate. | 08-19-2010 |
20110108708 | DIGITAL CAMERA WITH MULTIPLE PIPELINE SIGNAL PROCESSORS - A method includes sampling a first intensity of light with a first array of photo detectors of a digital camera. A second intensity of light is sampled with a second array of photo detectors of the digital camera. A first channel processor coupled to the first array of photo detectors generates a first image using first array data which is representative of the first intensity of light sampled by the first array of photo detectors. A second channel processor coupled to the second array of photo detectors generates a second image using second array data which is representative of the second intensity of light sampled by the second array of photo detectors. The first array of photo detectors, the second array of photo detectors, the first channel processor, and the second channel processor are integrated on or in a semiconductor substrate. | 05-12-2011 |
20120104526 | IMAGER MODULE OPTICAL FOCUS AND ASSEMBLY METHOD - An imager apparatus and methods are described. An embodiment of an imager module includes a plurality of groups of optical lenses, a lens frame, and at least one associated lens barrel configured to position and hold the plurality of groups of optical lenses. At least one of the groups of optical lenses is movable with respect to at least one other group of optical lenses for achieving optical focus. The imager module includes an integrated circuit (IC) imager die in proximity to the plurality of lenses, the imager die containing at least one image capture microelectronic device. | 05-03-2012 |
20120218435 | LARGE DYNAMIC RANGE CAMERAS - A digital camera includes a plurality of channels and a processing component operatively coupled to the plurality of channels. Each channel of the plurality of channels includes an optics component and a sensor that includes an array of photo-detectors. The processing component is configured to separately control an integration time of each channel, where a first integration time of a first channel is less than a second integration time of a second channel. The processing component is also configured to combine data from the plurality of channels to generate an image. | 08-30-2012 |
20130076928 | LARGE DYNAMIC RANGE CAMERAS - A digital camera includes a plurality of channels and a processing component operatively coupled to the plurality of channels. Each channel of the plurality of channels includes an optics component and a sensor that includes an array of photo-detectors. The processing component is configured to separately control an integration time of each channel, where a first integration time of a first channel is less than a second integration time of a second channel. The processing component is also configured to combine data from the plurality of channels to generate an image. | 03-28-2013 |
20130277533 | DIGITAL CAMERA WITH MULTIPLE PIPELINE SIGNAL PROCESSORS - A method includes sampling a first intensity of light with a first array of photo detectors of a digital camera. A second intensity of light is sampled with a second array of photo detectors of the digital camera. A first channel processor coupled to the first array of photo detectors generates a first image using first array data which is representative of the first intensity of light sampled by the first array of photo detectors. A second channel processor coupled to the second array of photo detectors generates a second image using second array data which is representative of the second intensity of light sampled by the second array of photo detectors. The first array of photo detectors, the second array of photo detectors, the first channel processor, and the second channel processor are integrated on or in a semiconductor substrate. | 10-24-2013 |
Patent application number | Description | Published |
20100213027 | Conveyor-Based Memory-Module Tester with Elevators Distributing Moving Test Motherboards Among Parallel Conveyors For Testing - A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader-unloader to an elevator. The elevator raises or lowers the motherboards to different levels in a conveyor stack with multiple levels of conveyors each with many test stations. The motherboards move along conveyors in the conveyor stack until reaching test stations. A retractable connector from the test station extends to make contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns. | 08-26-2010 |
20100218050 | Parking Structure Memory-Module Tester that Moves Test Motherboards Along a Highway for Remote Loading/Unloading - A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors. | 08-26-2010 |
20110050268 | Parking Structure Memory-Module Tester that Moves Test Motherboards Along a Highway for Remote Loading/Unloading - A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors. | 03-03-2011 |
20110193585 | CONVEYOR-BASED MEMORY-MODULE TESTER WITH ELEVATORS DISTRIBUTING MOVING TEST MOTHERBOARDS AMONG PARALLEL CONVEYORS FOR TESTING - A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader-unloader to an elevator. The elevator raises or lowers the motherboards to different levels in a conveyor stack with multiple levels of conveyors each with many test stations. The motherboards move along conveyors in the conveyor stack until reaching test stations. A retractable connector from the test station extends to make contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns. | 08-11-2011 |
20110298486 | Parking Structure Memory-Module Tester that Moves Test Motherboards Along a Highway for Remote Loading/Unloading - A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors. | 12-08-2011 |
Patent application number | Description | Published |
20090305249 | METHOD OF DETECTING CYP2A6 GENE VARIANTS - The present invention relates to methods for amplifying various regions of the CYP2A6 gene. Methods are provided for amplifying one or more fragments of the CYP2A6 gene in a single tube. The methods can identify mutations, deletion, duplication, and/or rearrangement in a sample containing the CYP2A6 gene. | 12-10-2009 |
20100317017 | CYSTIC FIBROSIS GENE MUTATIONS - The present invention provides novel mutations of the CFTR gene related to cystic fibrosis or to conditions associated with cystic fibrosis. Also provided are probes for detecting the mutant sequences. Methods of identifying if an individual has a genotype containing one or more mutations in the CFTR gene are further provided. | 12-16-2010 |
20110008790 | CYSTIC FIBROSIS TRANSMEMBRANE CONDUCTANCE REGULATOR GENE MUTATIONS - The present invention provides novel mutations of the CFTR gene related to cystic fibrosis or to conditions associated with cystic fibrosis. Also provided are probes for detecting the mutant sequences. Methods of identifying if an individual has a genotype containing one or more mutations in the CFTR gene are further provided. | 01-13-2011 |
20120082982 | CYSTIC FIBROSIS GENE MUTATIONS - The present invention provides novel mutations of the CFTR gene related to cystic fibrosis or to conditions associated with cystic fibrosis. Also provided are probes for detecting the mutant sequences. Methods of identifying if an individual has a genotype containing one or more mutations in the CFTR gene are further provided. | 04-05-2012 |
20120141996 | CYSTIC FIBROSIS TRANSMEMBRANE CONDUCTANCE REGULATOR GENE MUTATIONS - The present invention provides novel mutations of the CFTR gene related to cystic fibrosis or to conditions associated with cystic fibrosis. Also provided are probes for detecting the mutant sequences. Methods of identifying if an individual has a genotype containing one or more mutations in the CFTR gene are further provided. | 06-07-2012 |
20130115595 | METHOD TO DETECT REPEAT SEQUENCE MOTIFS IN NUCLEIC ACID - Methods for determining the presence or absence of expansion of CGG repeat sequence in the FMR1 gene presence or absence of expansion of CCG repeat sequence in the FMR2 gene are provided. The methods are useful in identifying an individual with normal/intermediate, versus premutation or full mutation allele of FMR1 gene and FMR2 gene due to the expansion of CGG repeats and CCG repeats in the 5′-untranslated region respectively. The methods are also useful for screening newborns for fragile X syndrome or for screening women to determine heterozygosity status with full premutation of the CCG repeat tract. The methods are also useful in estimating the premutation and full mutation carrier frequency and estimating the prevalence of FXTAS AND FXPOI in a population. The methods are simple, rapid and require small amount of sample. | 05-09-2013 |
20140178870 | CYSTIC FIBROSIS GENE MUTATIONS - The present invention provides novel mutations of the CFTR gene related to cystic fibrosis or to conditions associated with cystic fibrosis. Also provided are probes for detecting the mutant sequences. Methods of identifying if an individual has a genotype containing one or more mutations in the CFTR gene are further provided. | 06-26-2014 |
20150086996 | APTAMERS AND DIAGNOSTIC METHODS FOR DETECTING THE EGF RECEPTOR - The present invention provides aptamers that specifically bind to the EGF receptor in a sample, and diagnostic and analytical methods using those aptamers. In some embodiments, the aptamers include a 3′ cap. In some embodiments, the 3′ cap is an inverted deoxythymidine. In some embodiments the aptamers include a spacer and at least one moiety selected from the group consisting of binding pair member and a detectable label, wherein the spacer is attached to the 5′-end of the aptamer and the moiety is attached the 5′ end of the spacer. In some embodiments the spacer is hexaethylene glycol. In some embodiments, the binding pair member biotin. In some embodiments the detectable label is a fluorophore. | 03-26-2015 |
Patent application number | Description | Published |
20090024184 | COCHLEAR IMPLANT UTILIZING MULTIPLE-RESOLUTION CURRENT SOURCES AND FLEXIBLE DATA ENCODING - A programmable cochlear implant system utilizes multiple-resolution current sources and flexible data-encoding scheme for transcutaneous transmission. In certain embodiments, the number of current sources may be equal to or greater than 2, but equal or less than N−1, where N is the number of electrodes. The multi-resolution current source may introduce offset currents to achieve perceptually-based multiple resolutions with high resolution at low amplitudes and low resolution at high amplitudes. The flexible data-encoding scheme may allow arbitrary waveforms in terms of phase polarity, phase duration, pseudo-analog-waveform, while producing high-rate and high-temporal-precision stimulation. In one embodiment, a 2-current-source system may support simultaneous and non-simultaneous stimulation as well as monopolar, bipolar, pseudo-tripolar, and tripolar electrode configurations. | 01-22-2009 |
20120083859 | Cochlear Implant Utilizing Mutliple-Resolution Current Sources and Flexible Data Encoding - A programmable cochlear implant system utilizes multiple-resolution current sources and flexible data-encoding scheme for transcutaneous transmission. In certain embodiments, the number of current sources may be equal to or greater than 2, but equal or less than N−1, where N is the number of electrodes. The multi-resolution current source may introduce offset currents to achieve perceptually-based multiple resolutions with high resolution at low amplitudes and low resolution at high amplitudes. The flexible data-encoding scheme may allow arbitrary waveforms in terms of phase polarity, phase duration, pseudo-analog-waveform, while producing high-rate and high-temporal-precision stimulation. In one embodiment, a 2-current-source system may support simultaneous and non-simultaneous stimulation as well as monopolar, bipolar, pseudo-tripolar, and tripolar electrode configurations. | 04-05-2012 |