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Sun-Hwan
Sun-Hwan Hwang, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100317166 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 12-16-2010 |
| 20110027988 | METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE - Provided is a method for forming a buried word line in a semiconductor device. The method includes forming a trench by etching a pad layer and a substrate, forming a conductive layer to fill the trench, planarizing the conductive layer until the pad layer is exposed, performing an etch-back process on the planarized conductive layer, and performing an annealing process in an atmosphere of a nitride-based gas after at least one of the forming of the conductive layer, the planarizing of the conductive layer, and the performing of the etch-back process on the planarized conductive layer. | 02-03-2011 |
Sun-Hwan Hwang, Ichno-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20090189243 | SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a nitride layer formed on the oxide layer disposed on sidewalls of the trench and a high density plasma oxide layer formed on the nitride layer to fill the trench. | 07-30-2009 |
Sun-Hwan Hwang, Ichon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20090061602 | METHOD FOR DOPING POLYSILICON AND METHOD FOR FABRICATING A DUAL POLY GATE USING THE SAME - A method for doping polysilicon improves a doping profile during plasma doping and includes forming a silicon layer using two separate operations. After forming a first silicon layer, thermal annealing is performed to crystallize the first silicon layer, such that the uniformity of a doping concentration according to the depth of a layer inside is improved during plasma doping. Additionally, a doping concentration at the interface between a polysilicon layer and a gate oxide layer is increased. A by-product deposition layer is reduced, which is formed on the surface of a polysilicon layer due to the increase of a doping concentration in a polysilicon layer. As a result, the dopant loss, which is caused by the removing and cleansing of an ion implantation barrier used during doping, is reduced. | 03-05-2009 |
Sun-Hwan Lee, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090023764 | Use of Pyrimidinedione Derivative for Preventing or Treating Hepatitis C - A pyrimidinedione derivative of formula (I) or a pharmaceutically acceptable salt thereof exhibits excellent inhibitory activity against hepatitis C virus. | 01-22-2009 |