Patent application number | Description | Published |
20090148739 | DIRECT METHANOL FUEL CELL - A direct methanol fuel cell includes a cathode catalyst layer; an electrolyte membrane; an anode catalyst layer; a first fuel control layer that is water-repellent and conductive and that has pores; a second fuel control layer that is water-repellent and conductive and that has larger pores than the those of the first fuel control layer; a third fuel control layer that is water-repellent and conductive and that has smaller porous than those of the first fuel control layer and those of the second fuel control layer; and an anode GDL layer that is water-repellent and conductive, wherein the membrane and the layers above are arranged in the above order. | 06-11-2009 |
20090186257 | DIRECT METHANOL FUEL CELL SYSTEM, FUEL CARTRIDGE, AND MEMORY FOR FUEL CARTRIDGE - A fuel cartridge to be connected to a direct methanol fuel cell power generating device includes a spare fuel tank which stores a liquid fuel and is to be connected to the direct methanol fuel cell power generating device and a harmful substance trap member. The spare fuel tank stores a liquid fuel and is to be connected to the direct methanol fuel cell power generating device. The harmful substance trap member is fixed to the spare fuel tank and is to be connected to the direct methanol fuel cell power generating device. The harmful substance trap member contains a harmful substance trap material which traps gaseous harmful substances exhausted from the direct methanol fuel cell power generating device. | 07-23-2009 |
20090246589 | FUEL CELL CATALYST, PROCESS FOR PREPARATION OF THE SAME, AND MEMBRANE ELECTRODE ASSEMBLY AND FUEL CELL EMPLOYING THE CATALYST - The present invention provides a catalyst having high activity and excellent stability, a process for preparation of the catalyst, a membrane electrode assembly, and a fuel cell. The catalyst of the present invention comprises an electronically conductive support and catalyst fine particles. The catalyst fine particles are supported on the support and are represented by the formula (1): Pt | 10-01-2009 |
Patent application number | Description | Published |
20080213971 | Semiconductor device having dual-STI and manufacturing method thereof - A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved. | 09-04-2008 |
20090065841 | SILICON OXY-NITRIDE (SiON) LINER, SUCH AS OPTIONALLY FOR NON-VOLATILE MEMORY CELLS - An improved contact etch stop liner (CESL) is provided, to reduce stress effects in NVM cells using a nitride charge-trapping layer (such as NROM). SiON (silicon oxy-nitride) may be used in lieu of SiN (silicon nitride), for the CESL. Or, the CESL may be processed to be discontinuous, to reduce stress effects, using either conventional SiN (silicon nitride) or SiON. Or, the CESL layer may be eliminated entirely, to reduce stress effects. | 03-12-2009 |
20110057287 | SEMICONDUCTOR DEVICE HAVING DUAL-STI AND MANUFACTURING METHOD THEREOF - A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved. | 03-10-2011 |
20140177316 | NON-VOLATILE MEMORY SYSTEM WITH RESET VERIFICATION MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state. | 06-26-2014 |
20140177317 | NON-VOLATILE MEMORY SYSTEM WITH POWER REDUCTION MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory system including: providing a resistive storage element having a transformation layer; activating a write driver, coupled to the resistive storage element, for applying a bias voltage to the transformation layer; monitoring a resistance of the resistive storage element by a sense amplifier; and detecting a conductive thread, formed in the transformation layer, by the sense amplifier for reducing a level of the bias voltage. | 06-26-2014 |
Patent application number | Description | Published |
20100032839 | ELECTRODE STRUCTURE, SEMICONDUCTOR ELEMENT, AND METHODS OF MANUFACTURING THE SAME - According to the present invention, there is provided an electrode structure which includes: a nitride semiconductor layer; an electrode provided over the nitride semiconductor layer; and an electrode protective film provided over the electrode, wherein the nitride semiconductor layer contains a metal nitride containing Hb, Hf or Zr as a constitutive element, the electrode has a portion having a metal oxide containing Ti or V as a constitutive element formed therein, and the electrode protective film covers at least a portion of the electrode, and contains a protective layer having Au or Pt as a constitutive element. | 02-11-2010 |
20100200863 | ELECTRODE STRUCTURE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THOSE - A first layer containing Ti as a constituent element, a second layer containing Nb as a constituent element, and a third layer containing Au as a constituent element are formed on a GaN substrate 11. Thereafter, the GaN substrate 11 and the first to third layers are kept at 700° C. or higher and at 1300° C. or lower. This allows a metal oxide of Ti to be distributed to extend from the interface between the GaN substrate 11 and the electrode 14 over to the inside of the electrode 14. Further, a metal nitride of Nb is formed in the inside of the GaN substrate 11. The metal nitride of Nb will be distributed to extend from the inside of the electrode 14 over to the inside of the GaN substrate 11. | 08-12-2010 |
20120028456 | ELECTRODE STUCTURE, SEMICONDUCTOR ELEMENT, AND METHODS OF MANUFACTURING THE SAME - According to the present invention, there is provided an electrode structure which includes: a nitride semiconductor layer; an electrode provided over the nitride semiconductor layer; and an electrode protective film provided over the electrode, wherein the nitride semiconductor layer contains a metal nitride containing Nb, Hf or Zr as a constitutive element, the electrode has a portion having a metal oxide containing Ti or V as a constitutive element formed therein, and the electrode protective film covers at least a portion of the electrode, and contains a protective layer having Au or Pt as a constitutive element. | 02-02-2012 |