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Sumeet Mathur

Sumeet Mathur, Andhra Pradesh IN

Patent application numberDescriptionPublished
20100058349System and Method for Efficient Machine Selection for Job Provisioning - A method for efficient machine selection for job provisioning includes receiving a job request to perform a job using an unspecified server machine and determining one or more job criteria needed to perform the job from the job request. The method further includes providing a list of one or more server machines potentially operable to perform the job. For each server machine on the list of one or more server machines, a utilization value, one or more job criteria satisfaction values, and an overall suitability value are determined. The overall suitability value for each server machine is determined from the one or more job criteria satisfaction values and the utilization value, and may include a numeric degree to which each server machine is suitable for performing the job. Furthermore, the overall suitability value for each server machine may be included on a list of one or more overall suitability values.03-04-2010
20100271956System and Method for Identifying and Managing Service Disruptions Using Network and Systems Data - A method for identifying disruptions using network and systems data includes receiving resource utilization information for a network component at a first time and receiving resource utilization information for the network component at a second time. The method also includes identifying a resource utilization pattern for the network component, predicting a resource utilization for the network component at a third time based on the resource utilization pattern, and determining whether the predicted resource utilization will breach a utilization threshold for the network component.10-28-2010
20100274621Method and System for Integration of Systems Management with Project and Portfolio Management - A method for scheduling an information technology (IT) project includes receiving a project request at an interface and determining one or more tasks associated with the project request. The method also includes identifying one or more hardware components coupled to a network operable to perform each of the one or more tasks and retrieving a schedule for each of the identified hardware components. The method further includes selecting a hardware component to perform each of the one or more tasks scheduling each of the selected hardware components to perform each of the one or more tasks.10-28-2010

Sumeet Mathur, Bangalore IN

Patent application numberDescriptionPublished
20080272949METHODS AND APPARATUS TO CONTROL CURRENT STEERING DIGITAL TO ANALOG CONVERTERS - Methods and apparatus to control current steering digital to analog converters are described herein. In one example, a digital to analog converter includes a first unit cell including a positive output and a negative output, wherein the positive output of the first unit cell and the negative output of the first unit cell comprise substantially equal magnitudes and wherein the positive and negative outputs of the first unit cell are substantially one hundred eighty degrees out of phase; and a second unit cell including a positive output and a negative output, wherein the positive output of the second unit cell is substantially zero when the negative output of the second unit cell is non-zero.11-06-2008
20090009219Reducing Power Consumption In An Amplification Stage Driving A Sample And Hold Circuit While Maintaining Linearity - An input signal to be sampled by a sample and hold circuit is amplified separately by two amplifiers. The output of the first amplifier is provided to a boost circuit to maintain the impedance of a sampling switch contained in a signal dependent boost switch substantially constant. The output of the second amplifier is sampled via the sampling switch, and the sample is stored in a storage element. The second amplifier drives a reduced load, and may be implemented as a low bandwidth, low power amplifier to reduce overall power consumption.01-08-2009
20100164606DC BIASING CIRCUIT FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR - A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.07-01-2010
20100164611LEAKAGE INDEPENDENT VRY LOW BANDWIDTH CURRENT FILTER - A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit.07-01-2010
20100253563CAPACITOR BASED DIGITAL TO ANALOG CONVERTER LAYOUT DESIGN FOR HIGH SPEED ANALOG TO DIGITAL CONVERTER - A method and system for capacitor based digital to analog converter design layout for high speed analog to digital converter are provided. The method includes arranging a plurality of metal plates to form the capacitor. Each of the plurality of metal plates includes a driven plate and a common plate. The method also includes generating a plurality of interconnects in the common plate and extending the driven plate over the plurality of interconnects. Further, the method includes shielding the common plate by the driven plate. The system includes an analog to digital converter. The analog to digital converter also includes capacitor based digital to analog converter and digital logic for controlling digital operations in the analog to digital converter. The capacitor based digital to analog converter includes a plurality of capacitors, and a comparator for comparing the analog output from the digital to analog converter with a ground potential.10-07-2010

Patent applications by Sumeet Mathur, Bangalore IN