Patent application number | Description | Published |
20090001438 | Isolation of MIM FIN DRAM capacitor - In one embodiment, a capacitor comprises a substrate, a first electrically insulating layer over the substrate, a fin comprising a semiconducting material over the first electrically insulating layer, a cap formed from a silicide material on the first semiconducting fin, a first electrically conducting layer over the first electrically insulating layer and adjacent to the fin, a second electrically insulating layer adjacent to the first electrically conducting layer and a second electrically conducting layer adjacent to the second electrically insulating layer. | 01-01-2009 |
20090057648 | High Hole Mobility P-Channel Ge Transistor Structure on Si Substrate - The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 03-05-2009 |
20090090976 | PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY - A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths. | 04-09-2009 |
20090140301 | REDUCING CONTACT RESISTANCE IN P-TYPE FIELD EFFECT TRANSISTORS - Reducing contact resistance in p-type field effect transistors is generally described. In one example, an apparatus includes a first semiconductor substrate, a first noble metal film including palladium (Pd) coupled with the first semiconductor substrate, a second noble metal film including platinum (Pt) coupled with the first noble metal film, and a third metal film including an electrically conductive metal coupled with the second noble metal film, wherein the first, second, and third metal films form one or more contacts having reduced specific contact resistance between the first semiconductor substrate and the one or more contacts. | 06-04-2009 |
20090166680 | Unity beta ratio tri-gate transistor static radom access memory (SRAM) - In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate. | 07-02-2009 |
20090168498 | Spacer patterned augmentation of tri-gate transistor gate length - In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes. | 07-02-2009 |
20100258908 | ISOLATION OF MIM FIN DRAM CAPACITOR - In one embodiment, a capacitor comprises a substrate, a first electrically insulating layer over the substrate, a fin comprising a semiconducting material over the first electrically insulating layer, a cap formed from a suicide material on the first semiconducting fin, a first electrically conducting layer over the first electrically insulating layer and adjacent to the fin, a second electrically insulating layer adjacent to the first electrically conducting layer and a second electrically conducting layer adjacent to the second electrically insulating | 10-14-2010 |
20100327261 | HIGH HOLE MOBILITY P-CHANNEL GE TRANSISTOR STRUCTURE ON SI SUBSTRATE - The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 12-30-2010 |
20110299326 | TFET BASED 4T MEMORY DEVICES - A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction. | 12-08-2011 |
20120106236 | TFET BASED 6T SRAM CELL - Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines. | 05-03-2012 |
20150043260 | POWER RECTIFIER USING TUNNELING FIELD EFFECT TRANSISTOR - A power rectifier includes a stage having a first Tunneling Field-Effect Transistor (“TFET”) having a source, a gate, and a drain, a second TFET having a source, a gate, and a drain, a third TFET having a source, a gate, and a drain, and a fourth TFET having a source, a gate, and a drain such that the source of the first TFET, the source of the second TFET, the gate of the third TFET, and the gate of the fourth TFET are connected, the gate of the first TFET, the gate of the second TFET, the source of the third TFET and the source of the fourth TFET are connected, the drain of the first TFET and the drain of the third TFET are connected, and the drain of the second TFET and the drain of the fourth TFET are connected. Alternative embodiments are also disclosed. | 02-12-2015 |