Patent application number | Description | Published |
20110068347 | Nitride Semiconductor Structure and Method of Making Same - A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth. | 03-24-2011 |
20110069729 | Vertical Surface Emitting Semiconductor Device - A semiconductor light emitting device includes a pump light source, a gain structure, and an out-coupling mirror. The gain structure is comprised of InGaN layers that have resonant excitation absorption at the pump wavelength. Light from the pump light source causes the gain structure to emit light, which is reflected by the out-coupling mirror back to the gain structure. A distributed Bragg reflector causes internal reflection within the gain structure. The out-coupling mirror permits light having sufficient energy to pass therethrough for use external to the device. A frequency doubling structure may be disposed between the gain structure and the out-coupling mirror. Output wavelengths in the deep-UV spectrum may be achieved. | 03-24-2011 |
20110069730 | Semiconductor Laser with Integrated Contact and Waveguide - A semiconductor light-emitting device has, in place of a traditional separate cladding layer and contact structure, a non-epitaxial contact and waveguide layer. The non-epitaxial contact and waveguide layer is formed of a conductive material and such that it has a recess therein and over the injection region. Air filling the region together with appropriate choice of material for the non-epitaxial contact and waveguide layer creates desired lateral waveguiding. Metallic silver in one choice for this material. The recess may also be filled with a low-loss material having a refractive index higher than that of the material forming the non-epitaxial contact and waveguide layer. Transparent conductive oxides (e.g., indium tin oxide (ITO), zinc oxide (ZnO), etc.), appropriate metal (e.g., gold), or a composite comprising a conductive oxide and a metal, provide low absorption in the UV and near-IR wavelengths of interest, and are thus good candidate materials for within the recess. | 03-24-2011 |
20110150017 | Relaxed InGaN/AlGaN Templates - A relaxed InGaN template employs a GaN or InGaN nucleation layer grown at low temperatures on a conventional base layer (e.g., sapphire). The nucleation layer is typically very rough and multi-crystalline. A single-crystal InGaN buffer layer is then grown at normal temperatures. Although not necessary, the buffer layer is typically undoped, and is usually grown at high pressures to encourage planarization and to improve surface smoothness. A subsequent n-doped cap layer can then be grown at low pressures to form the n-contact of a photonic or electronic device. In some cases, a wetting layer—typically low temperature AlN—is grown prior to the nucleation layer. Other templates, such as AlGaN on Si or SiC, are also produced using the method of the present invention. | 06-23-2011 |
20110281424 | Relaxed InGaN/AlGaN Templates - A relaxed InGaN template is formed by growing a GaN or InGaN nucleation layer at low temperatures on a conventional base layer (e.g., sapphire). The nucleation layer is typically very rough and multi-crystalline. A single-crystal InGaN buffer layer is then grown at normal temperatures on the nucleation layer. Although not necessary, the buffer layer is typically undoped, and is usually grown at high pressures to encourage planarization and to improve surface smoothness. A subsequent n-doped cap layer can then be grown at low pressures to form the n-contact of a photonic or electronic device. In some cases, a wetting layer—typically low temperature AlN—is grown prior to the nucleation layer. Other templates, such as AlGaN on Si or SiC, are also produced using the method of the present invention. | 11-17-2011 |
Patent application number | Description | Published |
20110068347 | Nitride Semiconductor Structure and Method of Making Same - A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth. | 03-24-2011 |
20110069729 | Vertical Surface Emitting Semiconductor Device - A semiconductor light emitting device includes a pump light source, a gain structure, and an out-coupling mirror. The gain structure is comprised of InGaN layers that have resonant excitation absorption at the pump wavelength. Light from the pump light source causes the gain structure to emit light, which is reflected by the out-coupling mirror back to the gain structure. A distributed Bragg reflector causes internal reflection within the gain structure. The out-coupling mirror permits light having sufficient energy to pass therethrough for use external to the device. A frequency doubling structure may be disposed between the gain structure and the out-coupling mirror. Output wavelengths in the deep-UV spectrum may be achieved. | 03-24-2011 |
20110069730 | Semiconductor Laser with Integrated Contact and Waveguide - A semiconductor light-emitting device has, in place of a traditional separate cladding layer and contact structure, a non-epitaxial contact and waveguide layer. The non-epitaxial contact and waveguide layer is formed of a conductive material and such that it has a recess therein and over the injection region. Air filling the region together with appropriate choice of material for the non-epitaxial contact and waveguide layer creates desired lateral waveguiding. Metallic silver in one choice for this material. The recess may also be filled with a low-loss material having a refractive index higher than that of the material forming the non-epitaxial contact and waveguide layer. Transparent conductive oxides (e.g., indium tin oxide (ITO), zinc oxide (ZnO), etc.), appropriate metal (e.g., gold), or a composite comprising a conductive oxide and a metal, provide low absorption in the UV and near-IR wavelengths of interest, and are thus good candidate materials for within the recess. | 03-24-2011 |
20110268143 | Vertical Surface Emitting Semiconductor Device - A semiconductor light emitting device includes a pump light source, a gain structure, and an out-coupling mirror. The gain structure is comprised of InGaN layers that have resonant excitation absorption at the pump wavelength. Light from the pump light source causes the gain structure to emit light, which is reflected by the out-coupling mirror back to the gain structure. A distributed Bragg reflector causes internal reflection within the gain structure. The out-coupling mirror permits light having sufficient energy to pass therethrough for use external to the device. A frequency doubling structure may be disposed between the gain structure and the out-coupling mirror. Output wavelengths in the deep-UV spectrum may be achieved. | 11-03-2011 |
20120225541 | Nitride Semiconductor Structure - A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth. | 09-06-2012 |
Patent application number | Description | Published |
20100156245 | COATING FOR ACTUATOR AND METHOD OF APPLYING COATING - A method includes applying a lip, comprised of a first material, along at least a portion of an actuator of an electronic device, and applying a coating, comprised of an elastic material, to cover a part of the actuator, the coating disposed to facilitate actuation of the actuator. | 06-24-2010 |
20100156844 | PORTABLE ELECTRONIC DEVICE AND METHOD OF CONTROL - A portable electronic device includes a touch-sensitive display and a piezoelectric actuator disposed and preloaded on a support and arranged to provide tactile feedback to the touch-sensitive display in response to an actuation signal. The touch-sensitive display may be biased toward the piezoelectric actuator to preload the piezoelectric actuator. | 06-24-2010 |
20110134059 | PIEZOELECTRIC ASSEMBLY - A piezoelectric assembly is described. In accordance with one embodiment, there is provided a piezoelectric assembly comprising: an electrode assembly; a signal electrical connector electrically connected to the electrode assembly; a reference electrical connector electrically connected to the electrode assembly; and a spacer positioned about a perimeter of the electrode assembly and disposed between the signal electrical connector and the reference electrical connector such that no electrical communication is provided between the signal electrical connector and the reference electrical connector through the spacer; wherein a humidity barrier space is defined between the signal electrical connector, the reference electrical connector and the spacer, and wherein the electrode assembly is disposed in the humidity barrier space. | 06-09-2011 |
20120199460 | BREATHABLE SEALED DOME SWITCH ASSEMBLY - A sealed dome switch assembly is provided to allow air to flow between the interior and the exterior of the dome switch during the collapse and recovery of the resilient dome shell. The sealed dome switch assembly comprises at least one vent leading between the interior space and the exterior space of the sealed dome switch, wherein the vent is covered by a membrane that is permeable to air and resilient to liquid (e.g. water) and small particles (e.g. dirt). A vent may also be used to network the interiors of a plurality of sealed dome switches to at least one exterior entranceway that is covered by the membrane. | 08-09-2012 |
20120205165 | INPUT DETECTING APPARATUS, AND ASSOCIATED METHOD, FOR ELECTRONIC DEVICE - An apparatus, and an associated method, forms a user interface permitting input of input instructions to an electronic device. Input commands are evidence by tactile input forces applied to a force receiving surface. Force sensing elements are positioned to sense indications of the tactile input force. The force sensing element is caused to exhibit a selected input parameter value through application of a selected force thereto by application of a tightening torque to a fastener positioned in proximity to the force sensing element. | 08-16-2012 |
20120281366 | Battery Retention System - A battery protection mechanism is provided within an electronic device. A door has a latch which fits into a latch retention-release mechanism in the base of the device. A spring under tension within a retention-release mechanism presses against the latch when the device is in a closed configuration. A foot attached to a button in the base of the device urges the door out of position upon depression or activation of the button. | 11-08-2012 |
20130084736 | LOW PROFILE ELECTRICAL CONNECTOR - An electrical device has a socket formed as a continuous integral portion of an outer case housing. Conductors connect an interior of the socket to circuits within the device, and may be integrally molded with the outer case housing. Separate case housings may be assembled together to form the socket. A resulting socket has a lower profile and a reduced impact to a height requirement within the case, and has a relatively greater strength attributable to the inherent robustness of the case. | 04-04-2013 |
20130118876 | BREATHABLE SEALED DOME SWITCH ASSEMBLY - A sealed dome switch assembly is provided to allow air to flow between the interior and the exterior of the dome switch during the collapse and recovery of the resilient dome shell. The sealed dome switch assembly comprises at least one vent leading between the interior space and the exterior space of the sealed dome switch, wherein the vent is covered by a membrane that is permeable to air and resilient to liquid (e.g. water) and small particles (e.g. dirt). A vent may also be used to network the interiors of a plurality of sealed dome switches to at least one exterior entranceway that is covered by the membrane. | 05-16-2013 |
20130276550 | INPUT DETECTING APPARATUS, AND ASSOCIATED METHOD, FOR ELECTRONIC DEVICE - An apparatus, and an associated method, forms a user interface permitting input of input instructions to an electronic device. Input commands are evidence by tactile input forces applied to a force receiving surface. Force sensing elements are positioned to sense indications of the tactile input force. The force sensing element is caused to exhibit a selected input parameter value through application of a selected force thereto by application of a tightening torque to a fastener positioned in proximity to the force sensing element. | 10-24-2013 |
Patent application number | Description | Published |
20150028384 | GaN TRANSISTORS WITH POLYSILICON LAYERS FOR CREATING ADDITIONAL COMPONENTS - A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer. | 01-29-2015 |
20150028390 | GaN DEVICE WITH REDUCED OUTPUT CAPACITANCE AND PROCESS FOR MAKING SAME - A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor. | 01-29-2015 |
20150034962 | INTEGRATED CIRCUIT WITH MATCHING THRESHOLD VOLTAGES AND METHOD FOR MAKING SAME - An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess. | 02-05-2015 |
Patent application number | Description | Published |
20090136496 | CHRONIC LYMPHOCYTIC LEUKEMIA PROGNOSIS AND TREATMENT - Provided herein are methods for identifying a subject afflicted with chronic lymphocytic leukemia who is responsive to treatment with a chemotherapeutic agent by detecting the presence or absence of at least one APOE4 allele in the subject, the presence of an APOE4 allele identifying the subject as responsive to the treatment. Also provided are methods of treating a subject afflicted with chronic lymphocytic leukemia, including administering an estrogenic agent, an androgen withdrawal agent, an apoE4 peptide or mimetic thereof, and/or a chemotherapeutic agent in an amount effective to treat said chronic lymphocytic leukemia. Methods of determining a prognosis for a patient diagnosed with chronic lymphocytic leukemia are also provided. In addition, methods for stratifying a subject into a subgroup of a clinical trial and methods for identifying a patient in a clinical trial of a treatment for chronic lymphocytic leukemia are herein provided. | 05-28-2009 |
20110189175 | CHRONIC LYMPHOCYTIC LEUKEMIA PROGNOSIS AND TREATMENT - Provided herein are methods for identifying a subject afflicted with chronic lymphocytic leukemia who is responsive to treatment with a chemotherapeutic agent by detecting the presence or absence of at least one APOE4 allele in the subject, the presence of an APOE4 allele identifying the subject as responsive to the treatment. Also provided are methods of treating a subject afflicted with chronic lymphocytic leukemia, including administering an estrogenic agent, an androgen withdrawal agent, an apoE4 peptide or mimetic thereof, and/or a chemotherapeutic agent in an amount effective to treat said chronic lymphocytic leukemia. Methods of determining a prognosis for a patient diagnosed with chronic lymphocytic leukemia are also provided. In addition, methods for stratifying a subject into a subgroup of a clinical trial and methods for identifying a patient in a clinical trial of a treatment for chronic lymphocytic leukemia are herein provided. | 08-04-2011 |