Patent application number | Description | Published |
20090059678 | Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device - In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well. | 03-05-2009 |
20090309149 | Memory cell arrangements and methods for manufacturing a memory cell arrangement - In an embodiment, a memory cell arrangement is provided which may include a charge storing memory cell comprising a first active area running along a first direction, a second active area disposed next to the charge storing memory cell, the second active area running along a second direction, the second direction being different from the first direction, and a select structure disposed above the second active area configured to control a current flow through the second active area. | 12-17-2009 |
20100038696 | Semiconductor Device and Method for Making Same - One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material. | 02-18-2010 |
20110070726 | Method For Making Semiconductor Device - One or more embodiments may relate to a method for making a semiconductor device, including: a method for making a semiconductor device, comprising: providing a substrate; forming a charge storage layer over the substrate; forming a control gate layer over the charge storage layer; forming a mask over the control gate layer; using the mask, etching the control gate layer and the charge storage layer; forming a select gate layer over the etched control gate layer and the etched charge storage layer; forming an additional layer over the select gate layer; etching the additional layer to form sidewall spacers over the select gate layer; and etching the select gate layer. | 03-24-2011 |
20120139581 | TRANSISTOR ARRANGEMENT AND INTERGRATED CIRCUIT - A transistor arrangement includes a switch transistor and a sense transistor. The switch transistor includes a charge storing structure and a control structure. The sense transistor includes a charge storing structure, a control structure and a select structure. The charge storing structure of the switch transistor is electrically connected to the charge storing structure of the sense transistor. The sense transistor is configured such that the select structure and the control structure of the sense transistor may be electrically controlled independently from one another. | 06-07-2012 |
20130033934 | Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device - In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well. | 02-07-2013 |
20140213049 | METHOD FOR PROCESSING A CARRIER, METHOD FOR FABRICATING A CHARGE STORAGE MEMORY CELL, METHOD FOR PROCESSING A CHIP, AND METHOD FOR ELECTRICALLY CONTACTING A SPACER STRUCTURE - A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material. | 07-31-2014 |
20150091109 | MAGNETIC SHIELDING OF PERPENDICULAR STT-MRAM - A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks. | 04-02-2015 |
20150249211 | MEMORY - A memory includes a first electrode and a second electrode formed within a first layer and includes a third electrode and a fourth electrode formed within a second layer. The memory includes a resistive-switching memory element and an antifuse element. The resistive-switching memory element includes a metal oxide layer and is disposed between the first electrode and the third electrode. The metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness. The antifuse element includes a dielectric layer and is disposed between the second electrode and the fourth electrode. The dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage. | 09-03-2015 |
20150255477 | CHIP AND AN ELECTRONIC DEVICE - A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material. | 09-10-2015 |
20150255509 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line. | 09-10-2015 |
20150372230 | METHOD OF FORMING A MEMORY AND METHOD OF FORMING A MEMORY ARRAY - A method of forming a memory includes forming a first electrode and a second electrode within a first layer over a semiconductor substrate, forming a resistive-switching memory element and an antifuse element over the first layer, wherein the resistive-switching memory element includes a metal oxide layer and is electrically contacting the first electrode, wherein the metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness, wherein the antifuse element includes a dielectric layer and is electrically contacting the second electrode, and wherein the dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage, and forming a third electrode and a fourth electrode within a second layer over the resistive-switching memory element and the antifuse element, wherein the third electrode is electrically contacting the resistive-switching memory element and the fourth electrode is electrically contacting the antifuse element. | 12-24-2015 |