Patent application number | Description | Published |
20090106538 | System and Method for Implementing a Hardware-Supported Thread Assist Under Load Lookahead Mechanism for a Microprocessor - The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread. | 04-23-2009 |
20100262806 | Tracking Effective Addresses in an Out-of-Order Processor - Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag. | 10-14-2010 |
20100262807 | Partial Flush Handling with Multiple Branches Per Group - Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group. | 10-14-2010 |
20100262967 | Completion Arbitration for More than Two Threads Based on Resource Limitations - A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another. | 10-14-2010 |
20110302392 | INSTRUCTION TRACKING SYSTEM FOR PROCESSORS - A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group. | 12-08-2011 |
20120278595 | DETERMINING EACH STALL REASON FOR EACH STALLED INSTRUCTION WITHIN A GROUP OF INSTRUCTIONS DURING A PIPELINE STALL - During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from a plurality of functional units of the processor, a plurality of finish reports including completion reasons for a plurality of separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the plurality of finish reports. Once the monitoring unit receives a complete indicator from the completion unit, indicating the completion of the next to complete instruction group, the monitoring unit stores each determined stall reason aligned with each next to finish indicator in memory. | 11-01-2012 |
20130305022 | Speeding Up Younger Store Instruction Execution after a Sync Instruction - Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction. | 11-14-2013 |
20130346731 | INSTRUCTION TRACKING SYSTEM FOR PROCESSORS - Instructions are tracked in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group. | 12-26-2013 |
20140101416 | DETERMINING EACH STALL REASON FOR EACH STALLED INSTRUCTION WITHIN A GROUP OF INSTRUCTIONS DURING A PIPELINE STALL - During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from a plurality of functional units of the processor, a plurality of finish reports including completion reasons for a plurality of separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the plurality of finish reports. Once the monitoring unit receives a complete indicator from the completion unit, indicating the completion of the next to complete instruction group, the monitoring unit stores each determined stall reason aligned with each next to finish indicator in memory. | 04-10-2014 |
20140143523 | SPECULATIVE FINISH OF INSTRUCTION EXECUTION IN A PROCESSOR CORE - In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation. | 05-22-2014 |
Patent application number | Description | Published |
20080251120 | Thin Film Solar Cell and Manufacturing Method - The present invention relates to a thin film solar cell and a method of manufacturing such cells. In particular the invention relates to the use of a composite back contact ( | 10-16-2008 |
20080254202 | Method and Apparatus for In-Line Process Control of the Cigs Process - An in-line production apparatus and a method for composition control of copper indium gallium diselenide (CIGS) solar cells fabricated by a co-evaporation deposition process. The deposition conditions are so that a deposited Cu-excessive overall composition is transformed into to a Cu-deficient overall composition, the final CIGS film. Substrates with a molybdenum layer move through the process chamber with constant speed. The transition from copper rich to copper deficient composition on a substrate is detected by using sensors which detect a physical parameter related to the transition. A preferred embodiment sensors are provided that detect the composition of elements in the deposited layer. A controller connected to the sensors adjusts the fluxes from the evaporant sources in order provide a CIGS layer with uniform composition and thickness over the width of the substrate. | 10-16-2008 |
20100181088 | ELECTRICAL FEED-THROUGH - The present invention provides an electrical feed-through ( | 07-22-2010 |
20100233841 | THIN-FILM SOLAR CELL - Thin-film solar cells of the CIGS-type use two integrally formed buffer layers, a first ALD Zn(O,S) buffer layer on top of the CIGS-layer and a second ALD ZnO-buffer layer on top of the first buffer layer. Both buffer layers are deposited in the same process step using ALD (atom layer deposition). The technology also relates to a method of producing the cell and a process line for manufacturing of the cell structure. | 09-16-2010 |
20110088750 | SELECTIVE REMOVAL AND CONTRACTING OF THIN FILM SOLAR CELLS - A method for manufacturing a thin film solar cell device including a CIGS based thin film solar cell module ( | 04-21-2011 |
20130104965 | SOLAR CELL MODULE AND MANUFACTURING METHOD THEREFOR | 05-02-2013 |
20140007809 | METHOD AND APPARATUS FOR IN-LINE PROCESS CONTROL OF THE CIGS PROCESS - An in-line production apparatus and a method for composition control of copper indium gallium diselenide (CIGS) solar cells fabricated by a co-evaporation deposition process. The deposition conditions are so that a deposited Cu-excessive overall composition is transformed into to a Cu-deficient overall composition, the final CIGS film. Substrates with a molybdenum layer move through the process chamber with constant speed. The transition from copper rich to copper deficient composition on a substrate is detected by using sensors which detect a physical parameter related to the transition. Preferred embodiment sensors are provided that detect the composition of elements in the deposited layer. A controller connected to the sensors adjusts the fluxes from the evaporant sources in order provide a CIGS layer with uniform composition and thickness over the width of the substrate. | 01-09-2014 |