Patent application number | Description | Published |
20130095636 | PROCESS FOR PRODUCING AT LEAST ONE DEEP TRENCH ISOLATION - A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation. | 04-18-2013 |
20130099322 | METHOD FOR MANUFACTURING INSULATED-GATE TRANSISTORS - A method for defining an insulating area in a semiconductor substrate, including a step of forming of a bonding layer on the walls and the bottom of a trench defined in the substrate. A step of passivation of the apparent surface of said bonding layer, at least close to the surface of said semiconductor substrate. | 04-25-2013 |
20130099329 | METHOD FOR MANUFACTURING INSULATED-GATE MOS TRANSISTORS - A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate. | 04-25-2013 |
20130121070 | Memory Device - A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor. | 05-16-2013 |
20130157562 | WIRELESS DEVICE PAIRING - A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit. | 06-20-2013 |
20130164658 | PROCESS AND SYSTEM FOR DESIGNING A PHOTOLITHOGRAPHY MASK AND A LIGHT SOURCE - A method for designing a photolithography mask and a light source may include designing an initial photolithography mask and an initial light source using an initial target pattern corresponding to a desired target pattern in a resist layer. The method may also include designing a new target pattern and designing a new photolithography mask and/or a new light source using the new target pattern. | 06-27-2013 |
20130180562 | TUNNEL-EFFECT POWER CONVERTER - A tunnel-effect power converter including first and second electrodes having opposite surfaces, wherein the first electrode includes protrusions extending towards the second electrode. | 07-18-2013 |
20130181220 | METHOD FOR ESTIMATING THE DIFFUSION LENGTH OF METALLIC SPECIES WITHIN A THREE-DIMENSIONAL INTEGRATED STRUCTURE, AND CORRESPONDING THREE-DIMENSIONAL INTEGRATED STRUCTURE - A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations. | 07-18-2013 |