Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Steven F.
Steven F. Borsand, Deerfield, IL US
| Patent application number | Description | Published |
|---|---|---|
| 20100191642 | System and Method for Dynamic Quantity Orders in an Electronic Trading Environment - A system and method for dynamic quantity orders in an electronic trading environment are described. According to one method, a dynamic quantity order includes a price, a desired order quantity and a percentage associated with an estimated order quantity that will be filled in an order queue. When the order is received at an electronic exchange, the order is sorted into a pro-rata order queue, and the exchange may estimate a potential order quantity that will be filled in the order queue at the price based on the defined percentage. Subsequently, the exchange may then increase the order quantity of the dynamic quantity order so that if the estimated number of fills occurs, the order quantity of the dynamic quantity order will be filled. | 07-29-2010 |
| 20110040672 | System and Method for Dynamic Quantity Orders in an Electronic Trading Environment - A system and method for dynamic quantity orders in an electronic trading environment are described. According to one method, a dynamic quantity order includes a price, a desired order quantity and a percentage associated with an estimated order quantity that will be filled in an order queue. When the order is received at an electronic exchange, the order is sorted into a pro-rata order queue, and the exchange may estimate a potential order quantity that will be filled in the order queue at the price based on the defined percentage. Subsequently, the exchange may then increase the order quantity of the dynamic quantity order so that if the estimated number of fills occurs, the order quantity of the dynamic quantity order will be filled. | 02-17-2011 |
Steven F. Brown, Huntsville, AL US
| Patent application number | Description | Published |
|---|---|---|
| 20100045864 | Twisted pair communications line system - A transmission system for transmitting analog color video signals wherein a cable comprising multiple twisted pairs is employed, and certain of these pairs are coupled to carry selected color signals as a function of the delay provided by particular twist rates. In certain instances, selected signal delay devices are connected in circuit with certain twisted pairs. By such an arrangement, it has been found that relatively long distances between a computer and a monitor may be spanned by relatively low-cost, twisted pair cable commonly used for telephone communications. | 02-25-2010 |
Steven F. Chorian, Canton, MI US
| Patent application number | Description | Published |
|---|---|---|
| 20090051325 | AUTOMOTIVE POWER SYSTEM AND METHOD OF CONTROLLING SAME - A power source is electrically connected with a battery and an electrical load. The power source has an output voltage and provides current for the battery and electrical load. A charging voltage for the battery is determined based on temperature of the battery. An offset voltage is determined based on the provided current to the battery. The output voltage is determined based on the charging and offset voltages. | 02-26-2009 |
| 20100117593 | AUTOMOTIVE VEHICLE POWER SYSTEM - An energy storage system for an automotive vehicle includes a plurality of energy storage units electrically connected in series and a plurality of bi-directional energy converters each having first and second sides. Each of the first sides is electrically connected with one of the plurality of energy storage units. The system also includes another energy storage unit. The second sides of the plurality of bi-directional energy converters are electrically connected in parallel with the another energy storage unit. Each of the bi-directional energy converters is capable of transferring energy between the first and second sides. | 05-13-2010 |
| 20110013322 | AUTOMOTIVE VEHICLE CHARGE PORT WITH FAULT INTERRUPT CIRCUIT - An automotive vehicle includes a charge port integrated with the vehicle. The charge port includes electrical contacts configured to receive electrical power from an electric grid, and a fault interrupt circuit electrically connected with the electrical contacts. | 01-20-2011 |
| 20110082607 | System And Method For Balancing A Storage Battery For An Automotive Vehicle - A system and method is provided for balancing a storage battery for an automotive vehicle. The battery is of the type including a plurality of storage cells. The system includes a thermoelectric device and a controller. The thermoelectric device receives thermal energy and converts the thermal energy into electric energy. The controller determines a subset of the storage cells in the battery to be charged based on an amount of electric charge in each of the storage cells. Furthermore, the controller causes the electric energy to be distributed to each storage cell in the subset in an effort to balance the battery in the vehicle. | 04-07-2011 |
Steven F. Criscione, Raleigh, NC US
| Patent application number | Description | Published |
|---|---|---|
| 20100282891 | CABLE SPOOL WITH HEIGHT ADJUSTMENT CAPABILITY AND METHOD OF PERFORMING THE SAME - A spool and method of adjusting the same are disclosed. The spool is configured to provide a retainer for cable. The may include an upper flange, a lower flange, a plurality of access slots, a center portion, and a plurality of support legs. The support legs are configured to support the spool at a first distance above a securing surface, the support legs being adjustable to provide at least one additional distance that is different from the first distance. | 11-11-2010 |
Steven F. Harris, La Jolla, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100180051 | SYSTEM, APPARATUS, AND METHOD FOR FAST STARTUP OF USB DEVICES - Exemplary embodiments are directed to fast enumeration of a device in a USB system including a USB device and a USB host. The USB device includes two device descriptors, a memory for holding firmware for operation of the USB device, and a controller for executing the firmware. A first device descriptor is for enumerating the USB device in a firmware-loading mode and a second device descriptor is for enumerating the USB device in an operational mode. The USB host controls a first enumeration of the USB device using the first device descriptor. After the first enumeration, the USB host receives a re-enumerate indicator from the USB device and controls a second enumeration of the USB device using the second device descriptor. | 07-15-2010 |
| 20100274998 | METHOD AND SYSTEM FOR PROVIDING A DATA MODULE LOCK TO DEVICE HARDWARE - Systems and methods for confirming that a circuit card is compatible with a computer in which it is installed includes accessing a list of compatible circuit cards stored in the computer's nonvolatile memory, determining if the circuit card is included in the list of compatible circuit cards; and storing operating software on the circuit card only if the circuit card is included in the list of compatible circuit cards. The list of compatible circuit cards can be the Plug-and-Play Identification (PnP ID) list stored in the computer's BIOS data. Power may be removed from the circuit card if the circuit card is not include in the list of compatible circuit cards. | 10-28-2010 |
Steven F. Hoysan, Cypress, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080202164 | Isopipe design feature to reduce sag - Disclosed is an isopipe for use in the manufacture of sheet glass by, and more specifically to an isopipe designed to control sag during use, as well as a method for reducing the sag of an isopipe used in a fusion process for molten glass. In one embodiment, the isopipe comprises a cavity that extends at least partially through the refractory body of the isopipe along its longitudinal length. The cavity has varying cross-sections configured such that, for at least a portion of the length of the isopipe, the load bending moment is greater than or generally equal to the gravity bending moment. In one embodiment, the neutral axis varies along the length of the cavity and has a similar profile to that of the gravity bending moment diagram. | 08-28-2008 |
| 20100104486 | High Throughput Pressure Resistant Microfluidic Devices - A microfluidic device, comprising wall structures formed of a consolidated frit material positioned between and joined to two or more spaced apart substrates formed of a second material with the wall structures defining one or more fluidic passages between the substrates, has at least one passage with a height in a direction generally perpendicular to the substrates of greater than one millimeter, preferably greater than 1.1 mm, or than 1.2 mm, or than as much as 1.5 mm or more, and may have a non three-dimensionally tortuous portion of the at least one passage, in which the wall structures have an undulating shape such that no length of wall structure greater than 3 centimeters or greater than 2 centimeters, or greater than 1 centimeter, or even no length at all, is without a radius of curvature. A device may also include the undulations without the height. | 04-29-2010 |
Steven F. Hoysan US
| Patent application number | Description | Published |
|---|---|---|
| 20080202165 | Process to preserve isopipe during coupling - Methods for reducing stress on an isopipe during manufacture of a drawn glass sheet are disclosed including a method comprising providing an isopipe having a root, heating the isopipe to a predetermined temperature, maintaining the isopipe at the predetermined temperature for a period of time sufficient to relieve at least a portion of a tensile stress on the isopipe root, coupling the isopipe to a down-corner, and then providing glass to the isopipe. Also disclosed is a method comprising heating an isopipe such that the temperature difference between the weir and the root of the isopipe, after heating and prior to coupling, is less than about 100° C. A method comprising application of a compressive force to the ends of an isopipe root during heating is also disclosed. | 08-28-2008 |
Steven F. Miller, Wyndmoor, PA US
| Patent application number | Description | Published |
|---|---|---|
| 20100305774 | System for Generating Cost-Efficient Low Emission Energy - A method of economically substituting higher-priced clean energy sources for lower-price energy sources with negative environmental attributes by using a portion of the return on investment in a portfolio of residential, commercial, institutional or industrial energy efficiency measures to offset the cost of higher-priced, clean energy. Proceeds from investments and the monetization of the environmental benefits of the invention would are used to subsidize the cost of natural gas-fired plants so that they can economically displace coal-fired plants or other types of plants with similar negative environmental attributes as a source for base load power generation. | 12-02-2010 |
Steven F. Oakland, Colchester, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20080256405 | COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS - A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip. | 10-16-2008 |
| 20080284459 | Testing Using Independently Controllable Voltage Islands - A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test. | 11-20-2008 |
| 20080288841 | SYSTEM AND METHODS OF BALANCING SCAN CHAINS AND INSERTING THE BALANCED-LENGTH SCAN CHAINS INTO HIERARCHICALLY DESIGNED INTEGRATED CIRCUITS. - A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes estimating or calculating a maximum scan chain length L and creating a maximum number of scan chains of length L in each hierarchical block. The method further includes distributing remaining scan bits in each hierarchical block into additional scan chains, and creating chip-level scan chains by using the scan chains of maximum length L and by forming additional chip-level scan chains of maximum length L by distributing the additional scan chains of maximum length LR, plus any remaining top-level scan bits, among the additional chip-level scan chains of maximum length L. | 11-20-2008 |
| 20090055696 | MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) - Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock. | 02-26-2009 |
| 20100088561 | FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS - A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency. | 04-08-2010 |
| 20100088562 | FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS - A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency. | 04-08-2010 |
Steven F. Oakland, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20110055650 | Hold Transition Fault Model and Test Generation Method - A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0. | 03-03-2011 |
| 20110154141 | METHOD TO TEST HOLD PATH FAULTS USING FUNCTIONAL CLOCKING - A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse. | 06-23-2011 |
Steven F. Schossberger, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20080235846 | WRIST COVERING AND METHOD OF MAKING THE SAME - The present application is directed to a wrist covering designed to be worn over the gloved hand and arm-sleeve of a user. The wrist covering comprises a flexible, generally tubular member extending from a first opening, designed to fit around the forearm of the user, to a second opening, designed to fit around the hand of the user. The first opening has a larger circumference than the second opening. The wrist covering further includes a thumb aperture in the tubular member proximate to the second opening. A first fastener is positioned on the tubular member in a manner that allows tightening of the tubular member around the user's hand. A second fastener is positioned on the tubular member in a manner that allows tightening of the tubular member around the user's wrist. A third fastener is positioned on the tubular member in a manner that allows tightening of the tubular member around the user's forearm. A method of making the wrist covering is also disclosed. | 10-02-2008 |
Steven F. Sciamanna, Orinda, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080293685 | SPIRO AND OTHER DERIVATIVES OF DIAMONDOIDS POSSESSING THERAPEUTIC ACTIVITY IN THE TREATMENT OF VIRAL DISORDERS - This invention relates to diamondoid derivatives which exhibit therapeutic activity. Specifically, the diamondoid derivatives herein exhibit therapeutic effects in the treatment of viral disorders. Also provided are methods of treatment, prevention and inhibition of viral disorders in a subject in need. | 11-27-2008 |
| 20080300317 | DIAMONDOID DERIVATIVES POSSESSING THERAPEUTIC ACTIVITY IN THE TREATMENT OF VIRAL DISORDERS - This invention relates to diamondoid derivatives which exhibit therapeutic activity. Specifically, the diamondoid derivatives herein exhibit therapeutic effects in the treatment of viral disorders. Also provided are methods of treatment, prevention and inhibition of viral disorders in a subject in need. | 12-04-2008 |
| 20090029067 | METHOD FOR PRODUCING AMORPHOUS CARBON COATINGS ON EXTERNAL SURFACES USING DIAMONDOID PRECURSORS - The invention relates to a method for forming high sp | 01-29-2009 |
| 20090159498 | INTERGRATED PROCESS FOR IN-FIELD UPGRADING OF HYDROCARBONS - A process is provided for in-field upgrading of heavy hydrocarbons such as whole heavy oil, bitumen, and the like using supercritical water. | 06-25-2009 |
| 20090176035 | METHOD FOR PRODUCING DIAMOND-LIKE CARBON COATINGS USING DIAMONDOID PRECURSORS ON INTERNAL SURFACES - The invention relates to a method for forming high sp | 07-09-2009 |
Steven F. Zwinger, Poway, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080256398 | Using EMI signals to facilitate proactive fault monitoring in computer systems - A system that monitors electromagnetic interference (EMI) signals to facilitate proactive fault monitoring in a computer system is presented. During operation, the system receives EMI signals from one or more antennas located in close proximity to the computer system. The system then analyzes the received signals to proactively detect anomalies during operation of the computer system. | 10-16-2008 |
| 20090306920 | COMPUTER SYSTEM WITH INTEGRATED ELECTROMAGNETIC-INTERFERENCE DETECTORS - Embodiments of a system that determines a condition associated with an integrated circuit disposed on a circuit board are described. During operation, the system receives electromagnetic-interference (EMI) signals from one or more antennas while the integrated circuit is operating, where the one or more antennas are disposed on the circuit board. Then, the system analyzes the received EMI signals to determine the condition. | 12-10-2009 |
| 20100033922 | CONTROLLING A COOLING FAN FOR A STORAGE ARRAY - Some embodiments of the present invention provide a system that controls a cooling fan for a storage array. During operation, an input-output (I/O) metric of the storage array is monitored. Then, the cooling fan is controlled based on the I/O metric. | 02-11-2010 |
| 20100121788 | GENERATING A UTILIZATION CHARGE FOR A COMPUTER SYSTEM - Some embodiments of the present invention provide a system that generates a utilization charge for a computer system. First, a set of performance parameters of the computer system are monitored. Next, a power utilization of the computer system is inferred based on the set of performance parameters and a power-utilization model. Then, a utilization charge is generated based on the power utilization of the computer system. | 05-13-2010 |
| 20100284781 | MITIGATING MECHANICAL VIBRATIONS CAUSED BY A FAN IN A COMPUTER SYSTEM - One embodiment provides a system that mitigates vibrations caused by cooling fans in a computer system. More specifically, the system includes a cooling fan mechanically coupled to the chassis of the computer system, wherein vibrations generated by the cooling fan are coupled to the chassis. The system also includes an actuation mechanism that creates a relative displacement between the cooling fan and the chassis when a control signal is applied to the actuation mechanism. The system additionally includes a detection mechanism which detects the relative displacement and generates a feedback signal which represents the relative displacement. The system further includes a control signal generation mechanism which converts the feedback signal into the control signal, which is subsequently applied to the actuation mechanism. When the control signal is applied to the actuation mechanism, the relative displacement between the cooling fan and the chassis vibrationally decouples the cooling fan from the chassis. | 11-11-2010 |
| 20100332185 | ANALYTICAL BANDWIDTH ENHANCEMENT FOR MONITORING TELEMETRIC SIGNALS - Some embodiments provide a system that analyzes telemetry data from a monitored system. During operation, the system obtains the telemetry data as a set of telemetric signals from the monitored system and groups the telemetry data into one or more clusters of correlated telemetric signals from the telemetric signals. Next, the system increases a bandwidth associated with monitoring the telemetric signals. To increase the bandwidth, the system omits one or more of the correlated telemetric signals from each of the clusters during sampling of the telemetric signals and estimates the omitted correlated telemetric signals by applying a nonlinear, nonparametric regression technique to the sampled telemetric signals. | 12-30-2010 |