Patent application number | Description | Published |
20130304954 | Dynamically Optimizing Bus Frequency Of An Inter-Integrated Circuit ('I2C') Bus - Optimizing an I | 11-14-2013 |
20130343197 | Operating A Demultiplexer On An Inter-Integrated Circuit ('I2C') Bus - Operating a demultiplexer on an I | 12-26-2013 |
20130346658 | Chip Select ('CS') Multiplication In A Serial Peripheral Interface ('SPI') System - Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output. | 12-26-2013 |
20130346835 | Detecting Data Transmission Errors In An Inter-Integrated Circuit ('I2C') System - Detecting data transmission errors in an I | 12-26-2013 |
20140071647 | INTEGRATED CIRCUIT RETENTION MECHANISM WITH RETRACTABLE COVER - A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site. | 03-13-2014 |
20140344487 | Auto-Switching Interfaces to Device Subsystems - A method auto-switches interfaces between a client computer and subsystems in a device under management. A first output bus from a first subsystem is coupled to a client computer via a multiplexer, wherein the first subsystem is a subsystem from multiple system subsystems in the device under management. A hardware subsystem bus monitor monitors all output busses from the multiple system subsystems for a predetermined event on a bus. In response to the predetermined event being detected on a second output bus from a second subsystem in the device under management, the multiplexor decouples the first output bus from the client computer and couples the second output bus to the client computer. | 11-20-2014 |
20150053020 | IDENTIFYING PHYSICAL LOCATIONS OF DEVICES WITHIN AN ELECTRONIC SYSTEM - A system comprises a plurality of fans, wherein each of the fans is configurable to run at a unique fan speed that is different from fan speeds of other fans from the plurality of fans. A plurality of variable-positioned devices, capable of being positioned at various locations within the system, are physically positioned such that airflow from one of the plurality of fans strikes a particular variable-positioned device. A plurality of anemometers, each of which is connected to a particular variable-positioned device, measure airflow across the variable-positioned devices. A system controller, which contains location information that identifies a physical position within the system of each of the plurality of fans, utilizes airflow readings from each of the anemometers to identify a physical location of each of the plurality of variable-positioned devices by matching physical locations of the fans to measured airflow across the variable-positioned devices. | 02-26-2015 |
20150058515 | Allocating Lanes In A Peripheral Connect Interface Express ('PCIe') Bus - Allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device. | 02-26-2015 |
20150058517 | ALLOCATING LANES IN A PERIPHERAL CONNECT INTERFACE EXPRESS ('PCIe') BUS - Allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device. | 02-26-2015 |