Patent application number | Description | Published |
20090125747 | Asymmetrical IO Method and System - An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins. | 05-14-2009 |
20090248941 | Peer-To-Peer Special Purpose Processor Architecture and Method - A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus. | 10-01-2009 |
20100088452 | Internal BUS Bridge Architecture and Method in Multi-Processor Systems - An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols. | 04-08-2010 |
20100088453 | Multi-Processor Architecture and Method - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols. | 04-08-2010 |
20130147815 | MULTI-PROCESSOR ARCHITECTURE AND METHOD - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols. | 06-13-2013 |
20130219134 | WRITE DATA MASK METHOD AND SYSTEM - A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command. | 08-22-2013 |
20130342481 | DISABLING DISPLAY LINES DURING INPUT SENSING PERIODS - Embodiments of the present invention generally provide a processing system for a display device having an integrated sensing device. The processing system includes a driver module coupled to a plurality of transmitter electrodes. Each transmitter electrode includes one or more common electrodes configured for display updating and input sensing. The driver module is configured for selecting a first display line set for display updating during a first display update period and driving the first display line set for display updating during the first display update period. The driver module is further configured for driving one or more transmitter electrodes of the plurality of transmitter electrodes for input sensing during a non-display update period and selecting a second display line set for display updating during a restart period. | 12-26-2013 |
20140327621 | MULTI-FUNCTION KEYS PROVIDING ADDITIONAL FUNCTIONS AND PREVIEWS OF FUNCTIONS - Methods and devices are provided that employ multi-function keys to present a preview of potential actions to be taken by user key presses. The input device includes a plurality of key assemblies having a touch sensitive surface. The processing system can sense when one or more respective key assemblies have been contacted or pressed by the object. When the one or more respective key assemblies has been contacted by the object, an indication of a potential action taken in the program is provided to the user. The method determines whether the one or more respective key assemblies have been contacted or pressed by an object. A potential action to be taken is determined and an indication of the potential action is provided. | 11-06-2014 |
20150074313 | INTERNAL BUS ARCHITECTURE AND METHOD IN MULTI-PROCESSOR SYSTEMS - An internal bus architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols. | 03-12-2015 |