Patent application number | Description | Published |
20100215055 | METHOD AND APPARATUS FOR USING MULTIPLE PROTOCOLS ON A COMMUNICATION LINK - Multiple protocols are utilized on a single communication link. Information received over the communication link includes a protocol identification field specifying if the communication link is to operate under a first protocol or a different protocol. The second device interprets information transferred on the communication link according to one of the first protocol and the other protocols according to the protocol identification field. | 08-26-2010 |
20110022818 | IOMMU USING TWO-LEVEL ADDRESS TRANSLATION FOR I/O AND COMPUTATION OFFLOAD DEVICES ON A PERIPHERAL INTERCONNECT - An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations. | 01-27-2011 |
20120144128 | CUSTOM ATOMICS USING AN OFF-CHIP SPECIAL PURPOSE PROCESSOR - An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache line. The apparatus further comprises an atomic program execution unit that is configured to execute the atomic program as a single atomic memory transaction with a guarantee of forward progress. | 06-07-2012 |
20120324139 | WIRELESS COMMUNICATION FOR POINT-TO-POINT SERIAL LINK PROTOCOL - A wireless communication link, such as a PCIe endpoint-to-endpoint communication link, can be configured as a link in the communication protocol hierarchy, such that the wireless communication link is assigned its own bus identifier, and communications are routed to the wireless communication segment by a switch module based on the bus number. The wireless communication link can also be associated with the same link as a downstream wireless communication module. By employing the wireless communication segment as a link features of the communication protocol can be conventionally implemented by the host and downstream devices. | 12-20-2012 |
20130007379 | SECURE AND VIRTUALIZABLE PERFORMANCE COUNTERS - A method includes updating contents of a value storage element indicating a number of occurrences of an event. The updating is based on contents of a match storage element storing event qualification information. The method includes providing the contents of the value storage element to a first software module executing on at least one processor. The providing is based on contents of a protect storage element indicating access information. In at least one embodiment, the method includes executing a first software module on the at least one processor in a first mode of operation. In at least one embodiment, the method includes executing a second software module on the at least one processor in a second mode of operation. In at least one embodiment, the second mode is more privileged than the first mode. | 01-03-2013 |
20130080714 | I/O MEMORY TRANSLATION UNIT WITH SUPPORT FOR LEGACY DEVICES - An apparatus, method, and medium are disclosed for managing memory access from I/O devices. The apparatus comprises a memory management unit configured to receive, from an I/O device, a request to perform a memory access operation to a system memory location. The memory management unit is configured to detect that the request omits a memory access parameter, determine a value for the omitted parameter, and cause the memory access to be performed using the determined value. | 03-28-2013 |
20130173834 | METHODS AND APPARATUS FOR INJECTING PCI EXPRESS TRAFFIC INTO HOST CACHE MEMORY USING A BIT MASK IN THE TRANSACTION LAYER STEERING TAG - Methods and apparatus are provided for implementing transaction layer processing (TLP) hint (TPH) protocols in the context of the peripheral component interconnect express (PCIe) base specification. The method allows an endpoint function associated with a PCI Express device to configure a steering tag header in the open systems interconnect (OSI) transaction layer to identify a particular processing resource that the requester desires to target, such as a specific processor or cache location within the execution core. A bit mask may be implemented by the hardware or operating system, for example, by embedding the bit mask in the steering tag header. The bit mask provides administrative oversight of the steering tag header configuration, to thereby mitigate unintended denial of service attacks or cache misses occasioned by aggressive steering tag configuration strategies employed by endpoint functions. | 07-04-2013 |
20130173837 | METHODS AND APPARATUS FOR IMPLEMENTING PCI EXPRESS LIGHTWEIGHT NOTIFICATION PROTOCOLS IN A CPU/MEMORY COMPLEX - Methods and apparatus are provided for implementing a lightweight notification (LN) protocol in the PCI Express base specification which allows an endpoint function associated with a PCI Express device to register interest in one or more cachelines in host memory, and to request an LN notification message from the CPU/memory complex when the content of a registered cacheline changes. The LN notification message can be unicast to a single endpoint using ID-based routing, or broadcast to all devices on a given root port. The LN protocol may be implemented in the CPU complex by configuring a queue or other data structure in system memory for LN use. An endpoint registers a notification request by setting the LN bit in a “read” request of an LN configured cacheline. | 07-04-2013 |
20130332634 | TUNNEL SUITABLE FOR MULTI-SEGMENT COMMUNICATION LINKS AND METHOD THEREFOR - A tunnel for a communication system includes first and second bridges. The first bridge has a first port adapted to couple to a first link and a second port, and has a first programmable bus number and a first programmable function number. The second bridge has a first port coupled to the second port of the first bridge, and a second port, and has a second programmable bus number and a second programmable function number. In a hoist enabled mode, the first bridge forwards a packet on the first link to the second bridge if the second programmable bus number is equal to the first programmable bus number, a bus number of the packet is equal to the first programmable bus number, and a function number of the packet is equal to the second programmable function number. | 12-12-2013 |
20130346655 | BUS AGENT CAPABLE OF SUPPORTING EXTENDED ATOMIC OPERATIONS AND METHOD THEREFOR - A bus protocol compatible requester includes a bus protocol port for transmitting bus protocol compatible requests to a bus protocol link, and an extended atomic operation generation system, coupled to the bus protocol port, for generating an extended atomic operation by using at least one bit in a field of a standard bus protocol request other than an opcode field, and providing the extended atomic operation to the bus protocol port for transmission to a completer. A bus protocol compatible completer includes a bus protocol port for receiving bus protocol compatible requests from a bus protocol link, and an extended atomic operation execution system, coupled to the bus protocol port, for decoding an extended atomic operation according to at least one bit in a field of a standard bus protocol request other than an opcode field, and executing the extended atomic operation according to the at least one bit. | 12-26-2013 |