Steinlesberger
Gernot Steinlesberger, Otterfing DE
Patent application number | Description | Published |
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20090046499 | INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ - An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells. | 02-19-2009 |
20090213830 | COMMUNICATION SYSTEM - A communication system is disclosed. In one embodiment, the communication system includes a communication device set up to execute a process, configured to put itself into an activated state or into a deactivated state at alternate times, receive time information in a first operating state of the activated state, take the received time information as a basis for ascertaining the later time at which useful information is transmitted to the communication device, receive the useful information at the later time in a second operating state of the activated state. Individual components of the communication device are able to be put into an activated state or into a deactivated state independently of one another. | 08-27-2009 |
20090268513 | MEMORY DEVICE WITH DIFFERENT TYPES OF PHASE CHANGE MEMORY - A memory includes a first memory device including an array of phase changing memory cells. The first memory device is of a first memory type. The integrated circuit includes a second memory device including an array of phase changing memory cells. The second memory device is of a second memory type that is different than the first memory type. The first and second memory devices are packaged together into a single memory device. | 10-29-2009 |
Gernot Steinlesberger, Otterfing AT
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20090199043 | ERROR CORRECTION IN AN INTEGRATED CIRCUIT WITH AN ARRAY OF MEMORY CELLS - An integrated circuit includes an array of memory cells, and an error correction code circuit configured to correct errors in data read from the array based at least in part on a map that identifies locations of erratic memory cells in the array. | 08-06-2009 |
Gernot Steinlesberger, Otterfing Bergham DE
Patent application number | Description | Published |
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20080197384 | Field Effect Transistor Arrangement - A field effect transistor arrangement includes an electrically insulating layer, a source region, a drain region and a channel region arranged between source region and drain region, wherein the source region, the drain region and the channel region are in each case arranged on or above the electrically insulating layer, and also a gate region having an electrically insulating gate layer and an electrically conductive gate layer, which adjoins the channel region or is arranged at a distance from the latter and which extends at least partly along the channel region, wherein the source region and the drain region are in each case produced from electrically conductive carbon, and wherein the channel region is produced from strained silicon. | 08-21-2008 |