Patent application number | Description | Published |
20080253179 | SEMICONDUCTOR DEVICE, AN ELECTRONIC DEVICE AND A METHOD FOR OPERATING THE SAME - A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state. | 10-16-2008 |
20080299722 | Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure - The present invention provides a method for forming a recessed channel transistor comprising the steps of:
| 12-04-2008 |
20080308870 | INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE - An integrated circuit is disclosed. One embodiment provides a field-effect transistor including a gate electrode, a channel region and a first source/drain region. The gate electrode may include a main section determining a first flat band voltage between the gate electrode and the channel region and a first lateral section that is in contact with the main section and that determines a second flat band voltage between the gate electrode and the first source/drain region. The first and second flat band voltages differ by at least 0.1 eV. | 12-18-2008 |
20090057778 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type. | 03-05-2009 |
20090129145 | Memory Cell Array Comprising Floating Body Memory Cells - A memory cell array includes a plurality of floating body memory cells, which are arranged in cell rows, and world lines, wherein each word line is configured to control memory cells associated with a pair of cell rows. The memory cell array also includes bitlines, wherein each bitline is electrically connected to an individual memory cell of each pair of the cell rows. | 05-21-2009 |
20090179262 | Floating Body Memory Cell with a Non-Overlapping Gate Electrode - An integrated circuit includes a memory cell with a transistor. The transistor includes first and second doped portions, and a third portion disposed between the first and second doped portions. The first and the second doped portions and the third portion are disposed in a semiconductor substrate. The transistor further includes a gate electrode adjacent to the third portion, the gate electrode being insulated from the third portion. The gate electrode does not overlap at least one of the first and second doped portions, and a line connecting the first and the second portions extends substantially perpendicular to a surface of the substrate. | 07-16-2009 |
20090213648 | Integrated Circuit Comprising a Thyristor and Method of Controlling a Memory Cell Comprising a Thyristor - An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal. | 08-27-2009 |
20090296449 | Integrated Circuit and Method of Operating an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit is provided including a plurality of resistivity changing memory elements and a plurality of memory element select devices, wherein the select devices are floating body select devices. | 12-03-2009 |
20100014372 | Semiconductor Device, an Electronic Device and a Method for Operating the Same - A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state. | 01-21-2010 |
20100110753 | Ferroelectric Memory Cell Arrays and Method of Operating the Same - An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices. | 05-06-2010 |