| Patent application number | Description | Published |
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| 20080203137 | SUBSTRATE BONDING METHODS AND SYSTEM INCLUDING MONITORING - Bonding methods and a bonding system including monitoring are disclosed. In one embodiment, a method of monitoring bonding a first and second substrate includes: providing a plurality of piezoelectric sensors to a substrate mounting stage of a substrate bonding system; and monitoring a force change measured by the plurality of piezoelectric sensors induced by a bond front between the first and second substrate during bonding. This method allows real time monitoring of the bonding quality and adjustment of the bonding process parameters. | 08-28-2008 |
| 20080206977 | METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR - Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. | 08-28-2008 |
| 20080217782 | METHOD FOR PREPARING 2-DIMENSIONAL SEMICONDUCTOR DEVICES FOR INTEGRATION IN A THIRD DIMENSION - A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired. | 09-11-2008 |
| 20090202952 | SUBLITHOGRAPHIC PATTERNING METHOD INCORPORATING A SELF-ALIGNED SINGLE MASK PROCESS - A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension. | 08-13-2009 |
| 20090251698 | METHOD AND SYSTEM FOR COLLECTING ALIGNMENT DATA FROM COATED CHIPS OR WAFERS - A process and system for determining alignment data for features on wafers or chips when a wafer or chip is substantially coated by an over bump applied material, e.g. a resin or film, and using that data to align the wafers or chips for subsequent operations such as dicing or joining. Position data for alignment is produced by identifying a location of an at least partially obscured feature by varying the depth of focus upon a work piece to determine an SNR approximating a maximum value from an image captured by optical scanning. An SNR above a threshold value can be employed. | 10-08-2009 |
| 20090259321 | System and Method for Virtual Control of Laboratory Equipment - A system for virtual control of electronic laboratory equipment includes a local computer system. One or more items of electronic laboratory equipment are connected to the local computer system. Each item of electronic laboratory equipment has a physical control panel including one or more displays or controls. A virtual control panel generation unit generates a virtual control panel accessible from a remote computer system. The virtual control panel is substantially similar to the physical control panel in appearance. A command interpretation unit monitors interaction between the remote user and the virtual control panel and generates electronic laboratory equipment commands for exploiting the functionality of the electronic laboratory equipment. | 10-15-2009 |
| 20100133616 | METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR - Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. | 06-03-2010 |
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| 20090050486 | Enhanced Magnetic Plating Method and Apparatus - An apparatus for plating a magnetic film on a substrate includes: a track including a plurality of stopping points along the track; a permanent magnet placed on the track such that the permanent magnet can be moved along the track towards and away from the stopping points; at least one plating tank positioned on the stopping point; and a removable high permeability iron flux concentrator inserted into gaps between the substrate and inside walls of the plating tank, substantially surrounding the substrate and extending around and under the substrate. | 02-26-2009 |
| 20100037933 | SOLAR CELL PANELS AND METHOD OF FABRICATING SAME - A solar cell panel and method of forming a solar cell panel. The method includes a: forming an electrically conductive bus bar on a top surface of a bottom cover plate; forming an electrically conductive contact frame proximate to a bottom surface of a top cover plate, the top cover plate transparent to visible light; and placing an array of rows and columns of solar cell chips between the bottom cover plate and the top cover plate, each solar cell chip of the array of solar cell chips comprising an anode adjacent to a top surface and a cathode adjacent to a bottom surface of the solar cell chip, the bus bar electrically contacting each anode of each solar cell chip of the array of solar cell chips and the contact frame contacting each anode of each solar cell chip of the array of solar cell chips. | 02-18-2010 |
| 20100037939 | METHODS OF FABRICATING SOLAR CELL CHIPS - A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips. | 02-18-2010 |
| 20100188774 | PLANAR MAGNETIC WRITER HAVING OFFSET PORTIONS - A magnetic head in one embodiment includes a bottom pole; a top pole positioned above a plane extending through the bottom pole and parallel to a plane of deposition of the bottom pole, wherein the top pole is at least partially offset from the bottom pole in a direction parallel to a plane of deposition of the top pole; a first write gap in the top pole; and a first coil for generating a magnetic flux across the first write gap. A method in one embodiment includes forming a bottom pole; forming a top pole above a plane extending through the bottom pole and parallel to a plane of deposition of the bottom pole, wherein the top pole is at least partially offset from the bottom pole in a direction parallel to a plane of deposition of the top pole, wherein at least one write gap is formed in the top pole; forming side poles for coupling the top and bottom poles; and forming a first coil for generating a magnetic flux across the first write gap. | 07-29-2010 |
| 20100297800 | SOLAR CELL PANELS AND METHOD OF FABRICATING SAME - A solar cell panel and method of forming a solar cell panel. The method includes a: forming an electrically conductive bus bar on a top surface of a bottom cover plate; forming an electrically conductive contact frame proximate to a bottom surface of a top cover plate, the top cover plate transparent to visible light; and placing an array of rows and columns of solar cell chips between the bottom cover plate and the top cover plate, each solar cell chip of the array of solar cell chips comprising an anode adjacent to a top surface and a cathode adjacent to a bottom surface of the solar cell chip, the bus bar electrically contacting each anode of each solar cell chip of the array of solar cell chips and the contact frame contacting each anode of each solar cell chip of the array of solar cell chips. | 11-25-2010 |
| 20100304519 | METHOD OF FABRICATING SOLAR CELL CHIPS - A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips. | 12-02-2010 |
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| 20100136323 | SYSTEM FOR THERMAL PROTECTION AND DAMPING OF VIBRATIONS AND ACOUSTICS - A protective shield for a device exposed to heat includes a granular fill layer, a nano particle layer, a metallic foam layer, a thermal barrier coating, or combinations thereof. The shield is configured for providing thermal resistance, and damping of vibrations, and acoustics to the device. | 06-03-2010 |
| 20110103987 | PUMP SYSTEM - The present invention provides a pump system comprising a bearing housing coupled to a pump liner, the pump liner defining a fluid conduit, the pump liner comprising a fluid inlet and a fluid outlet; and at least one rotor having a first rotor portion and a second rotor portion, the first rotor portion being disposed within the fluid conduit and the second rotor portion being disposed within the bearing housing; the first rotor portion comprising a first conveying stage adjacent to the bearing housing, and a second conveying stage adjacent to the first conveying stage, the first and second conveying stages being configured to convey a fluid, the first conveying stage being configured to convey the fluid from the bearing housing into the fluid conduit. The new pump systems rely on a dynamic restriction to reduce the need for mechanical seals between bearing housings and raw process fluid. | 05-05-2011 |
